14.9.16. Ich4-M Power-Up Sequence; Table 106. Ich4-M Power-Up Timing Specifications - Intel 852GME Design Manual

Platform Design Checklist

14.9.16. ICH4-M Power-up Sequence

Table 106. ICH4-M Power-up Timing Specifications

Sym
T173
T176
T177
T178
T181
T182/T183
T183a
T183b
T184
T185
T186
NOTES:
1. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay from
RTCRST# and the RSMRST# inactive to SUSCLK toggling may be as much as 1000 ms.
2. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs.
3. This transition is clocked off the 66-MHz CLK66. 1 CLK66 is approximately 15 ns.
4. It is not necessary for PWROK to be asserted before or after PM_VGATE is asserted. However, if PWROK is
asserted after PM_VGATE, it must be delayed 3-10 ms from PWRGD from the VR (which enables clock).
Similarly, if PM_VGATE is asserted after PWROK, it must be delayed 3-10 ms from PWRGD from the VR
(which enables clock).
5. Please refer to ICH4-M for latest specifications.
272
Description
VccSus supplies active to LAN_RST#,
RSMRST# inactive
Vcc1.5, Vcc3.3, VccHI supplies active to
PWROK, VGATE active
PWROK and VGATE active and SYS_RESET#
inactive to SUS_STAT# inactive
SUS_STAT# inactive to PCIRST# inactive
VccSus active to SLP_S5#, SUS_STAT# and
PCIRST# active
RSMRST# inactive to SUSCLK running,
SLP_S5# inactive
SLP_S5# inactive to SLP_S4# inactive
SLP_S4# inactive to SLP_S3# inactive
Vcc_CPU_IO active to STPCLK#, CPUSLP#
inactive, and CPU Frequency Strap signals high
PWROK and VGATE active and SYS_RESET#
inactive to SUS_STAT# inactive and CPU
Frequency Straps latched to strap values
CPU Reset Complete to Frequency Straps
signals unlatched from strap values
® ®
Intel 852GME, Intel 852GMV and Intel
Min Max Units
10 - ms
10 - ms
32 38 RTCCLK
1 3 RTCCLK
50 ns
110 ms
1 2 RTCCLK
1 2 RTCCLK
50 ns
32 38 RTCCLK
7 9 CLK66
®
852PM Chipset Platforms Design Guide
R
Notes
4
2
2
1
2
2
2
3