Intel 810A3 Manuals

Manuals and User Guides for Intel 810A3. We have 1 Intel 810A3 manual available for free PDF download: Design Manual

Intel 810A3 Design Manual (166 pages)

Chipset Platform

Brand: Intel | Category: Computer Hardware | Size: 1.02 MB

3
Table of Contents
11
Introduction
13
About This Design Guide
- 14
  Terminology and Definitions
- 19
  References
19
System Overview
- 20
  Graphics and Memory Controller Hub (GMCH)
20
Tv-Out
- 21
  I/O Controller Hub (82801AA ICH)
- 21
  System Configurations
21
Intel ® 810A3 Chipset
22
Platform Initiatives
- 22
  Hub Interface
- 22
  Manageability
23
Ac'97
- 24
  Low Pin Count (LPC) Interface
24
AC'97 with Audio and Modem Codec Connections
25
PGA370 Processor Design Guidelines
27
Electrical Differences for Flexible PGA370 Designs
28
PGA370 Socket Definition Details
28
Platform Pin Definition Comparison for Single Processor Designs
- 29
  Processor Pin Definition Comparison
31
Calculations for 100 Mhz Bus
32
Topology for 370-Pin Socket Designs with Single Ended Termination (SET)
32
Segment Descriptions and Lengths for Figure
32
Trace Width (Space Guidelines)
34
Routing for THRMDP and THRMDN
34
Routing Guidelines for Non-Agtl+ Signals
- 35
  Undershoot/Overshoot Requirements
- 35
  BSEL[1:0] Implementation for PGA370 Designs
35
BSEL[1:0] Circuit Implementation for PGA370 Designs
- 36
  CLKREF Circuit Implementation
- 36
  Undershoot/Overshoot Requirements
36
Examples for CLKREF Divider Circuit
36
Example Resistor Values for CLKREF Divider Circuit (3.3V Source)
- 37
  Connecting RESET# and RESET2# On a Flexible PGA370 Design
- 37
  Reset Strapping Options
37
RESET# Schematic for PGA370 Designs
- 38
  Voltage Regulation Differences
- 38
  Decoupling Guidelines for Flexible PGA370 Designs
38
Capacitor Placement On the Motherboard
- 39
  Thermal/Emi Differences
- 40
  Debug Port Changes
40
TAP Connector Comparison
41
SC242 Processor Design Guidelines
44
Calculations for 100 Mhz Bus
45
Determine General Topology and Layout
45
Solution Space
45
Intel ® Pentium ® III Processor and GMCH AGTL+ Parameters for
45
Segment Descriptions and Lengths for Figure
45
Trace Width:space Guidelines
46
Minimizing Crosstalk
46
Motherboard Layout Rules for Non-Agtl+ (CMOS) Signals
46
Routing Guidelines for Non-Agtl+ Signals
47
THRMDP and THRMDN
47
Additional Considerations
47
Routing for THRMDP and THRMDN
48
Motherboard Frequency Select for SC242 Designs
48
System Bus Frequency Selection Topology for SC242
49
Grounding Retention Mechanism (GRM)
- 49
  Motherboard Interfaces
49
Hole Locations and Keep-Out Zones for Support Components
50
Detailed Drawing of Minimum Ground Pad Size and Location
51
Layout and Routing Guidelines
53
General Recommendations
53
Nominal Board Stackup
54
Component Quadrant Layouts
54
Nominal Board Stackup
54
GMCH Quadrant Layout (Topview)
55
ICH 241-Ubga Quadrant Layout (Topview)
56
Intel 810A3 Chipset Component Placement
56
Uatx Placement Example for PGA370 Processors
57
System Memory Layout Guidelines
- 57
  System Memory Solution Space
57
System Memory Topologies
- 58
  System Memory Routing Example
58
System Memory Routing
- 59
  System Memory Connectivity
59
Display Cache Interface
- 60
  Display Cache Solution Space
60
Display Cache (Topology 2)
60
Display Cache (Topology 3)
60
Display Cache Routing (Topology 1)
60
Display Cache Routing (Topology 2)
60
Display Cache Routing (Topology 3)
61
Hub Interface
61
Display Cache (Topology 4)
61
Hub Interface Signal Routing Example
61
Display Cache Routing (Topology 4)
- 62
  Data Signals
- 62
  Strobe Signals
- 62
  HREF Generation/Distribution
- 63
  Compensation
63
Single Hub Interface Reference Divider Circuit
63
Locally Generated Hub Interface Reference Dividers
64
Ultra ATA/66
- 64
  IDE Routing Guidelines
64
IDE Min/Max Routing and Cable Lengths
65
Ultra ATA/66 Cable
66
Resistor Schematic for Primary IDE Connectors
66
Resistor Schematic for Secondary IDE Connectors
- 67
  Ultra ATA/66 Detection
68
Host-Side IDE Cable Detection
69
Host-Side IDE Cable Detection
- 70
  Audio/Modem Riser Card (AMR)
70
AC'97 Configuration Combinations
- 71
  AC'97 Routing
72
Tee Topology AC'97 Trace Length Requirements for ATX
72
Daisy-Chain Topology AC'97 Trace Length Requirements for ATX
- 73
  Motherboard Implementation
74
Usb
75
IOAPIC (I/O Advanced Programmable Interrupt Controller)
75
USB Data Signals
75
Recommended USB Trace Characteristics
76
Pci
76
Rtc
- 76
  RTC Crystal
76
PCI Bus Layout Example for 4 PCI Connectors
- 77
  External Capacitors
77
External Circuitry for the ICH RTC
- 78
  RTC Layout Considerations
- 78
  RTC External Battery Connection
78
A Diode Circuit to Connect RTC External Battery
- 79
  RTC External RTCRESET Circuit
- 79
  VBIAS DC Voltage and Noise Measurements
79
RTCRESET External Circuit for the ICH RTC
80
Processor PLL Filter Recommendation
- 80
  Topology
- 80
  Filter Specification
80
Filter Topology
- 82
  Recommendation for Intel Platforms
82
Using Discrete R
- 83
  Custom Solutions
83
No Discrete R
83
Core Reference Model
84
Ramdac/Display Interface
84
Schematic of RAMDAC Video Interface
- 85
  Reference Resistor (Rset) Calculation
- 85
  RAMDAC Board Design Guidelines
86
RAMDAC Component and Routing Guidelines
87
DPLL Filter Design Guidelines
87
Recommended RAMDAC Reference Resistor Placement and Connections
- 88
  Filter Specification
88
Recommended LC Filter Connection
- 89
  Recommended Routing/Component Placement
- 89
  Example LC Filter Components
89
DPLL LC Filter Component Example
90
Frequency Response (See Table 4-13)
90
Additional DPLL LC Filter Component Example
91
Resistance Values for Frequency Response Curves (See Figure 4-38)
95
Advanced System Bus Design
95
AGTL+ Design Guidelines
- 96
  Initial Timing Analysis
- 97
  Determine General Topology, Layout, and Routing Desired
- 97
  Pre-Layout Simulation
- 99
  Place and Route Board
100
Trace Width Space Guidelines
100
Host Clock Routing
- 101
  Post-Layout Simulation
101
PICD[1,0] Uni-Processor Topology
- 102
  Validation
103
Test Load Vs. Actual System Load
104
Theory
- 104
  Agtl
- 104
  Timing Requirements
- 105
  Cross-Talk Theory
105
Aggressor and Victim Networks
105
Transmission Line Geometry: (A) Microstrip (B) Stripline
107
More Details and Insight
- 107
  Textbook Timing Equations
- 108
  Effective Impedance and Tolerance/Variation
- 108
  Power/Reference Planes, PCB Stackup, and High Frequency Decoupling
109
One Signal Layer and One Reference Plane
109
Layer Switch with One Reference Plane
109
Layer Switch with Multiple Reference Planes (Same Type)
110
Layer Switch with Multiple Reference Planes
110
One Layer with Multiple Reference Planes
- 111
  Clock Routing
112
Definitions of Flight Time Measurements/Corrections and Signal Quality
- 112
  Ringback Levels
112
Intel ® Pentium ® III Processor and GMCH AGTL+ Parameters for
- 113
  VREF Guardband
- 113
  Overdrive Region
- 113
  Flight Time Definition and Measurement
113
Conclusion
113
Overdrive Region and V REF Guardband
115
Clocking
117
Clock Generation
118
Clock Architecture
119
Clock Routing Guidelines
119
Group Skew and Jitter Limits at the Pins of the Clock Chip
119
Signal Group and Resistor
120
Layout Dimensions
121
Different Topologies for the Clock Routing Guidelines
122
Capacitor Sites
122
Clock Power Decoupling Guidelines
122
Example of Capacitor Placement Near Clock Input Receiver
123
System Design Considerations
125
Power Delivery
- 125
  Intel 810A3 Chipset Power Delivery
- 126
  Intel ® 810A3 Chipset Power Delivery Architecture
127
Intel 810A3 Chipset Power Map
127
Super I/O
128
Intel 810A3 Chipset Voltage Regulator Specifications
- 129
  LED Indicator for S0-S5 States
130
Decoupling Guidelines
- 130
  VCC CORE Decoupling
- 130
  Phase Lock Loop (PLL) Decoupling
- 131
  82810A3 GMCH Decoupling Guidelines
- 132
  Ground Flood Planes
132
Thermal Design Power
132
82810A3 GMCH Power Plane Decoupling
133
Power Sequencing
133
G3-S0 Transistion
134
S0-S3-S0 Transition
135
S0-S5-S0 Transition
136
Power Sequencing Timing Definitions
137
Design Checklist
139
Design Review Checklist
- 139
  Design Checklist Summary
140
AGTL+ Connectivity Checklist for 370-Pin Socket Processors
141
CMOS Connectivity Checklist for 370-Pin Socket Processors
141
TAP Checklist for a 370-Pin Socket Processor
142
Miscellaneous Checklist for 370-Pin Socket Processors
143
AGTL+ Connectivity Checklist for SC242 Processors
144
CMOS Connectivity Checklist for SC242 Processors
144
TAP Checklist for SC242 Processors
144
Miscellaneous Checklist for SC242 Processors
145
Special Consideration Checklist
145
Clock Generator Checklist
146
ICH Checklist
147
ICH Checklist
148
GMCH Checklist
148
System Memory Checklist
149
Display Cache Checklist
149
LPC Super I/O Checklist
149
IDE Checklist
150
Clock Generator Checklist
150
FWH Flash BIOS Checklist
150
PCI Bus Checklist
151
USB / Keyboard / Mouse Checklist
151
AC'97 Checklist
152
Power Delivery Checklist
153
Pullup and Pulldown Resistor Values
153
Pullup Resistor Example
154
Rtc
154
Power Management Signals
155
PWRGOOD and PWROK Logic
- 156
  Power Button Implementation
159
Third-Party Vendor Information
159
Memory Vendors
159
Voltage Regulator Vendors
159
Flat Panel
160
Software DVD
161
TMDS Transmitters
161
TV Encoders
161
Combo TMDS Transmitters/Tv Encoders
161
LVDS Transmitter
165
PCI Devices and Functions
165
PCI Devices and Registers
166
PCI Devices/Functions/Registers/Interrupts
166
PCI Devices and Interrupts

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Intel 810A3 Manuals

Manuals and User Guides for Intel 810A3. We have 1 Intel 810A3 manual available for free PDF download: Design Manual

Intel 810A3 Design Manual (166 pages)

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