Intel 810A3 Manuals

Manuals and User Guides for Intel 810A3. We have 1 Intel 810A3 manual available for free PDF download: Design Manual

Intel 810A3 Design Manual (166 pages)

Chipset Platform

Brand: Intel | Category: Computer Hardware | Size: 1.02 MB

Table of Contents
3
Introduction
11
About this Design Guide
13
- Terminology and Definitions
  14
- References
  19
System Overview
19
- Graphics and Memory Controller Hub (GMCH)
  20
TV-Out
20
- I/O Controller Hub (82801AA ICH)
  21
- System Configurations
  21
Intel ® 810A3 Chipset
21
Platform Initiatives
22
- Hub Interface
  22
- Manageability
  22
Ac'97
23
- Low Pin Count (LPC) Interface
  24
AC'97 with Audio and Modem Codec Connections
24
PGA370 Processor Design Guidelines
25
Electrical Differences for Flexible PGA370 Designs
27
Platform Pin Definition Comparison for Single Processor Designs
28
- Processor Pin Definition Comparison
  29
PGA370 Socket Definition Details
28
Calculations for 100 Mhz Bus
31
Topology for 370-Pin Socket Designs with Single Ended Termination (SET)
32
Segment Descriptions and Lengths for Figure
32
Trace Width (Space Guidelines)
32
Routing for THRMDP and THRMDN
34
Routing Guidelines for Non-AGTL+ Signals
34
- Undershoot/Overshoot Requirements
  35
- BSEL[1:0] Implementation for PGA370 Designs
  35
BSEL[1:0] Circuit Implementation for PGA370 Designs
35
- CLKREF Circuit Implementation
  36
- Undershoot/Overshoot Requirements
  36
Examples for CLKREF Divider Circuit
36
Example Resistor Values for CLKREF Divider Circuit (3.3V Source)
36
- Connecting RESET# and RESET2# on a Flexible PGA370 Design
  37
- Reset Strapping Options
  37
RESET# Schematic for PGA370 Designs
37
- Voltage Regulation Differences
  38
- Decoupling Guidelines for Flexible PGA370 Designs
  38
Capacitor Placement on the Motherboard
38
- Thermal/Emi Differences
  39
- Debug Port Changes
  40
TAP Connector Comparison
40
SC242 Processor Design Guidelines
41
Calculations for 100 Mhz Bus
44
Segment Descriptions and Lengths for Figure
45
Trace Width:space Guidelines
45
Determine General Topology and Layout
45
Solution Space
45
Intel ® Pentium ® III Processor and GMCH AGTL+ Parameters for
45
Routing Guidelines for Non-AGTL+ Signals
46
Minimizing Crosstalk
46
Motherboard Layout Rules for Non-AGTL+ (CMOS) Signals
46
Routing for THRMDP and THRMDN
47
THRMDP and THRMDN
47
Additional Considerations
47
System Bus Frequency Selection Topology for SC242
48
Motherboard Frequency Select for SC242 Designs
48
Hole Locations and Keep-Out Zones for Support Components
49
Grounding Retention Mechanism (GRM)
49
- Motherboard Interfaces
  49
Detailed Drawing of Minimum Ground Pad Size and Location
50
Layout and Routing Guidelines
51
General Recommendations
53
Nominal Board Stackup
53
Nominal Board Stackup
54
GMCH Quadrant Layout (Topview)
54
Component Quadrant Layouts
54
ICH 241-Ubga Quadrant Layout (Topview)
55
Uatx Placement Example for PGA370 Processors
56
Intel 810A3 Chipset Component Placement
56
System Memory Layout Guidelines
57
- System Memory Solution Space
  57
System Memory Topologies
57
- System Memory Routing Example
  58
System Memory Routing
58
- System Memory Connectivity
  59
Display Cache Interface
59
- Display Cache Solution Space
  60
Display Cache Routing (Topology 1)
60
Display Cache Routing (Topology 2)
60
Display Cache Routing (Topology 3)
60
Display Cache (Topology 2)
60
Display Cache (Topology 3)
60
Hub Interface
61
Display Cache Routing (Topology 4)
61
- Data Signals
  62
- Strobe Signals
  62
- HREF Generation/Distribution
  62
- Compensation
  63
Display Cache (Topology 4)
61
Hub Interface Signal Routing Example
61
Single Hub Interface Reference Divider Circuit
63
Locally Generated Hub Interface Reference Dividers
63
Ultra ATA/66
64
- IDE Routing Guidelines
  64
IDE Min/Max Routing and Cable Lengths
64
Ultra ATA/66 Cable
65
Resistor Schematic for Primary IDE Connectors
66
Resistor Schematic for Secondary IDE Connectors
66
- Ultra ATA/66 Detection
  67
Host-Side IDE Cable Detection
68
Host-Side IDE Cable Detection
69
- Audio/Modem Riser Card (AMR)
  70
AC'97 Configuration Combinations
70
- AC'97 Routing
  71
Tee Topology AC'97 Trace Length Requirements for ATX
72
Daisy-Chain Topology AC'97 Trace Length Requirements for ATX
72
- Motherboard Implementation
  73
Usb
74
Recommended USB Trace Characteristics
75
IOAPIC (I/O Advanced Programmable Interrupt Controller)
75
USB Data Signals
75
Pci
76
Rtc
76
- RTC Crystal
  76
PCI Bus Layout Example for 4 PCI Connectors
76
- External Capacitors
  77
External Circuitry for the ich RTC
77
- RTC Layout Considerations
  78
- RTC External Battery Connection
  78
A Diode Circuit to Connect RTC External Battery
78
- RTC External RTCRESET Circuit
  79
- VBIAS DC Voltage and Noise Measurements
  79
RTCRESET External Circuit for the ich RTC
79
Processor PLL Filter Recommendation
80
- Topology
  80
- Filter Specification
  80
Filter Topology
80
- Recommendation for Intel Platforms
  82
Using Discrete R
82
- Custom Solutions
  83
No Discrete R
83
Core Reference Model
83
Ramdac/Display Interface
84
Schematic of RAMDAC Video Interface
84
- Reference Resistor (Rset) Calculation
  85
- RAMDAC Board Design Guidelines
  85
RAMDAC Component and Routing Guidelines
86
Recommended RAMDAC Reference Resistor Placement and Connections
87
- Filter Specification
  88
DPLL Filter Design Guidelines
87
Recommended LC Filter Connection
88
- Recommended Routing/Component Placement
  89
- Example LC Filter Components
  89
DPLL LC Filter Component Example
89
Frequency Response (See Table 4-13)
90
Additional DPLL LC Filter Component Example
90
Resistance Values for Frequency Response Curves (See Figure 4-38)
91
Advanced System Bus Design
95
AGTL+ Design Guidelines
95
Trace Width Space Guidelines
100
Host Clock Routing
100
- Post-Layout Simulation
  101
PICD[1,0] Uni-Processor Topology
101
- Validation
  102
Test Load Vs. Actual System Load
103
Theory
104
- Agtl
  104
- Timing Requirements
  104
- Cross-Talk Theory
  105
Aggressor and Victim Networks
105
Transmission Line Geometry: (A) Microstrip (B) Stripline
105
More Details and Insight
107
One Signal Layer and One Reference Plane
109
Layer Switch with One Reference Plane
109
Layer Switch with Multiple Reference Planes (same Type)
109
Layer Switch with Multiple Reference Planes
110
One Layer with Multiple Reference Planes
110
- Clock Routing
  111
Intel ® Pentium ® III Processor and GMCH AGTL+ Parameters for
112
- VREF Guardband
  113
- Overdrive Region
  113
- Flight Time Definition and Measurement
  113
Definitions of Flight Time Measurements/Corrections and Signal Quality
112
- Ringback Levels
  112
Conclusion
113
Overdrive Region and V REF Guardband
113
Clocking
115
Clock Generation
117
Clock Architecture
118
Clock Routing Guidelines
119
Group Skew and Jitter Limits at the Pins of the Clock Chip
119
Signal Group and Resistor
119
Layout Dimensions
120
Different Topologies for the Clock Routing Guidelines
121
Example of Capacitor Placement Near Clock Input Receiver
122
Capacitor Sites
122
Clock Power Decoupling Guidelines
122
System Design Considerations
123
Power Delivery
125
- Intel 810A3 Chipset Power Delivery
  125
- Intel ® 810A3 Chipset Power Delivery Architecture
  126
Super I/O
127
Intel 810A3 Chipset Power Map
127
Intel 810A3 Chipset Voltage Regulator Specifications
128
- LED Indicator for S0-S5 States
  129
Decoupling Guidelines
130
- VCC CORE Decoupling
  130
- Phase Lock Loop (PLL) Decoupling
  130
- 82810A3 GMCH Decoupling Guidelines
  131
- Ground Flood Planes
  132
82810A3 GMCH Power Plane Decoupling
132
Thermal Design Power
132
G3-S0 Transistion
133
Power Sequencing
133
S0-S3-S0 Transition
134
S0-S5-S0 Transition
135
Power Sequencing Timing Definitions
136
Design Checklist
137
Design Review Checklist
139
- Design Checklist Summary
  139
AGTL+ Connectivity Checklist for 370-Pin Socket Processors
140
CMOS Connectivity Checklist for 370-Pin Socket Processors
141
TAP Checklist for a 370-Pin Socket Processor
141
Miscellaneous Checklist for 370-Pin Socket Processors
142
AGTL+ Connectivity Checklist for SC242 Processors
143
CMOS Connectivity Checklist for SC242 Processors
144
TAP Checklist for SC242 Processors
144
Miscellaneous Checklist for SC242 Processors
144
Special Consideration Checklist
145
Clock Generator Checklist
145
ICH Checklist
146
ICH Checklist
147
GMCH Checklist
148
System Memory Checklist
148
Display Cache Checklist
149
LPC Super I/O Checklist
149
IDE Checklist
149
Clock Generator Checklist
150
FWH Flash BIOS Checklist
150
PCI Bus Checklist
150
USB / Keyboard / Mouse Checklist
151
AC'97 Checklist
151
Power Delivery Checklist
152
Pullup Resistor Example
153
Pullup and Pulldown Resistor Values
153
Rtc
154
Power Management Signals
154
PWRGOOD and PWROK Logic
155
- Power Button Implementation
  156
Memory Vendors
159
Voltage Regulator Vendors
159
Flat Panel
159
Third-Party Vendor Information
159
Software DVD
160
TMDS Transmitters
161
TV Encoders
161
Combo TMDS Transmitters/Tv Encoders
161
LVDS Transmitter
161
PCI Devices and Functions
165
PCI Devices and Registers
165
PCI Devices and Interrupts
166
PCI Devices/Functions/Registers/Interrupts
166

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