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CHAPTER 3
PROGRAMMING INFORMATION
3.1 INTRODUCTION
This chapter lists 1/0 address assignments, describes
the effects of hardware initialization, and provides
programming information for the Intel 8251 A
USART
(Universal
Synchronous/ Asynchronous
Receiver/Transmitter), the Intel 8253 PIT (Program-
mabie intervai Timer), and the on-board controi and
status registers.
A complete description of the Intel iAPX 432
General Data Processor (GDP)-its instruction set,
programming, and protection mechanisms-may be
found in the
iAPX 432 General Data Processor
Architecture Reference Manual,
Order
No.
171860-00 I.
3.2 MEMORY ADDRESSING
AND ACCESS
The iSBC 432/ 100 Processor Board contains no local
memory; all GDP memory accesses are processed
over the Multibus architecture. GDP physical
address references are translated into Multibus
memory read/write commands. Physical addresses
generated by the GDP are modified by an on-board
off set register to permit an Intellec or iSBC system
processor to share Multibus memory with the iSBC
432/ 100 processor.
When the GDP addresses memory (via the Multibus
bus) each GDP access request is implemented as one
or more 8/16-bit Multihus data transfers. Memory
access mechanisms are described in detail beginning
in paragraph 4-4. Briefly, to perform Multibus data
transfers, the iSBC 432/ 100 board must first gain
control of the bus. After addressing the correct
memory location and issuing a Memory Read or
Memory Write command, the processor board waits
until a Transfer Acknowledge (XACK/) is received
from the addressed memory module. When the data
transfer is completed, the iSBC 432/100 board
releases the bus to permit other masters to use it.
When a GDP access request specifies a multibyte
data transfer that must be translated into more than
one Multibus transfer, a "bus lock" feature permits
the processor board to retain Multibus control for
the complete sequence of Multibus transfers. This
feature eliminates the time required to release and
regain bus control between data transfers, thereby
increasing throughput and lowering Multibus band-
width requirements.
3.3
1/0
ADDRESSING AND ACCESS
GDP local address references are translated into
Multibus 1/0 read/write commands. All 1/0 port
accesses (including accesses to on-board devices)
occur via the Multibus bus. 1/0 ports physically
located on the iSBC 432/ 100 Processor Board are
logically situated on the bus. Any bus master may
access the board's 1/0 ports (listed in table 3-1). 1/0
address generation is performed in the same manner
as
memory
address
generation
(described
in
paragraph 4-5).
3.4 INITIALIZATION
The Multibus initialization signal line (INIT /), when
activated, resets the GDP and causes the 8251A
USART to enter an "idle" state waiting for a set of
Command Words to program the desired function.
The 8253 PIT is not affected by the INIT I signal.
In addition to the INIT I reset sequence, another
Multibus master may reset the GDP by writing the
processor reset flag (contained within the processor
control register-refer to table 3-1).
3.5 8251A USART PROGRAMMING
The USART converts parallel output data into a
serial output data format (e.g., IBM Bi-Sync) for
half- or full-duplex operation. The USART also con-
verts serial input data into parallel data format.
Prior to the start of data transmission or data recep-
tion, the USART must be loaded with a set of control
words. These control words, which define the com-
plete functional operation of the USART, must
immediately follow a reset (internal or external). The
control words are either Mode instructions or
Command instructions.
3.6 MODE INSTRUCTION FORMAT
The Mode instruction word defines the general
characteristics of the USART and must follow a reset
operation. Once the Mode instruction word has been
3-1
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