Address Space And Memory Partitions - Intel NIOS II Owner Reference Manual

3. Programming Model
NII-PRG | 2018.04.18
Distinct processes can use the same virtual address space. The process identifier,
concatenated with the virtual address, distinguishes identical virtual addresses in
separate processes. To determine the physical address, the Nios II MMU translates a
VPN to a PFN and then concatenates the PFN with the page offset. The bits in the page
offset are not translated.
Memory Protection
The Nios II MMU maintains read, write, and execute permissions for each page. The
TLB provides the permission information when translating a VPN. The operating
system can control whether or not each process is allowed to read data from, write
data to, or execute instructions on each particular page. The MMU also controls
whether accesses to each data page are cacheable or uncacheable by default.
Whenever an instruction attempts to access a page that either has no TLB mapping, or
lacks the appropriate permissions, the MMU generates an exception. The Nios II
processor's precise exceptions enable the system software to update the TLB, and
then re-execute the instruction if desired.
3.2.2.2. Memory Protection
The Nios II MMU maintains read, write, and execute permissions for each page. The
TLB provides the permission information when translating a VPN. The operating
system can control whether or not each process is allowed to read data from, write
data to, or execute instructions on each particular page. The MMU also controls
whether accesses to each data page are cacheable or uncacheable by default.
Whenever an instruction attempts to access a page that either has no TLB mapping, or
lacks the appropriate permissions, the MMU generates an exception. The Nios II
processor's precise exceptions enable the system software to update the TLB, and
then re-execute the instruction if desired.

3.2.3. Address Space and Memory Partitions

The MMU provides a 4-GB virtual address space, and is capable of addressing up to
4 GB of physical memory.
Note: The amount of actual physical memory, determined by the configuration of your
hardware system, might be less than the available 4 GB of physical address space.
3.2.3.1. Virtual Memory Address Space
The 4-GB virtual memory space is divided into partitions. The upper 2 GB of memory
is reserved for the operating system and the lower 2 GB is reserved for user
processes.
Table 8. Virtual Memory Partitions
Partition
I/O
0xE0000000
Kernel
0xC0000000
Kernel MMU
0x80000000
User
0x00000000
Virtual Address Range
–
0xFFFFFFFF
–
0xDFFFFFFF
–
0xBFFFFFFF
–
0x7FFFFFFF
Used By Memory Access
Operating system Bypasses TLB
Operating system Bypasses TLB
Operating system Uses TLB
User processes Uses TLB
User Mode Default Data
Access Cacheability
No Disabled
No Enabled
No Set by TLB
Set by TLB Set by TLB
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