Big And Little Endian Memory Transfers - Intel i86W Manual

Id.b
O(rO), r16
Id.b 1 (rO), r16
Id.b
2(rO), r16
Id.b
3("ll), r16
Id.b 4(rO), r16
Id.b 5(..0), r16
Id.b
6!,o), ~16
Id.b
7(rO), r16
Id.8 O(rO), r16
Id.8 2(rO), r16
Id.8
4(rO),
f1~
Id.8 6(rO), r16
Id.1 O(rO), r16
Id.l 4(rO), r16
ADDRESSING
MAIN MEMORY
.
~g~g ~
H G FED C B A
d63
dO
lITILE END IAN
BIG ENDIAN
BYTE ENABLES DATA BUS r16
BYTE ENABLES
DATA BUS
(BE#)
dO
A
d63 dO d63
~---------A~ p----~
D
B
C
B
C
D
4 E
E
5 F F
6 G
G
H H
d63 dO d63 dO
1:0
CJ[]
3:2
D C D C
5:4
F E F E
7:6 H G H G
d63 dO d63
dO
3:0
IH G
FED C B AI
~
7:4 H G F E
(BE#)
d63 dO
7
H
6 G
F
4 E
3
D
C
1
B
0 A
d63
dO
7:6
CJ
5:4 F E
3:2
. D C
1:0
BA
d63
dO
7:4
IHGFE D
C B AI
3:0
Figure 4-2. Big and Little Endian Memory Transfers
r16
d31 dO
H
G
E
D
C
B
A
d31
dO
0
F E
D C
B A
d31 dO
kd
DeB A
240329i
• A 64-bit value is aligned to an address divisible by eight when referenced in memory
(i.e. the three least significant address bits must be zero) or a data-access trap occurs.
• A 32-bit value is aligned to an address divisible by four when referenced in memory
(i.e. the two least significant address bits must be zero) or a data-access trap occurs.
• A 16-bit value is aligned to an address divisible by two when referenced in memory
(i.e. the least significant address bit must be zero) or a data-access trap occurs.
4.2 VIRTUAL ADDRESSING
When address translation is enabled, the i860 microprocessor maps instruction and data
virtual addresses into physical addresses before referencing memory. This address trans-
formation is compatible with that of the 386
™
microprocessor and implements the basic
features qeeded for page-oriented virtual-memory systems and page-level protection.
The address translation is optional. Address translation is in effect only when the ATE
bit of dirbase is set. This bit is typically set by the operating system during software
initialization. The ATE bit must be set if the operating system is to implement page-
oriented protection or page-oriented virtual memory.
4-2