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4.1.1
Layout Guidelines
Figure 4-3
memory controller. The Flash subsystem requires an external latch for address and data
demultiplexing on RAD[16:3]. The data is multiplexed on RAD[16:9].
Figure 4-3.
4 Mbyte Flash Memory System
80960RM/RN
Flash signal loading should not exceed 50 pF. If the system conforms to I
minimum 16 Mbit Flash such as Intel's 28F016SA is suggested.
All traces between the
4.1.2
Wait State Profiles
Table 4-2
Table 4-2.
ROM, SRAM, or Flash Wait State Profile Programming
Device Speed
Design Guide
illustrates how two Flash devices would interface to the
RALE
RAD[16:0]
ROE#
RWE#
RCE0#
RCE1#
RM/RN I/O processor
summarizes various wait state profiles of SRAM and writable non-volatile memory devices.
≤ 55 ns
≤ 115 ns
≤ 175 ns
Intel® i960® RM/RN I/O Processor
®
Intel
80960RM/RN Processor Memory Subsystem
A[2:0]
RAD[2:0]
A[8:3]
RAD[8:3]
A[22:17]
Latch
A[16:9]
RAD[16:9]
Latch
DQ[7:0]
*
and Flash/SRAM should not exceed 8 inches.
Address-to-Data Wait States
4
8
12
RM/RN I/O processor
with the
A[20:0]
OE#
Intel 28F016-70
WE#
16 Mbit Flash
DQ[7:0]
CE#
A[20:0]
OE#
Intel 28F016-70
WE#
16 Mbit Flash
DQ[7:0]
CE#
O specification, then a
2
Recovery Wait States
0
4
4
13
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