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Intel MultiProcessor Specification

Intel MultiProcessor Specification (97 pages)

Intel MultiProcessor Specification

Brand: Intel | Category: Computer Hardware | Size: 0 MB

Table of Contents

Revision History
3
Table of Contents
5
Chapter 1 Introduction

11
- Goals
  11
- Conceptual Overview
  11
  - Features of the Specification
    12
  - Scope
    12
  - Target Audience
    13
  - Organization of this Document
    13
- Memory Layout Conventions
  14
  - Conventions Used in this Document
    14
  - For more Information
    14
Chapter 2 System Overview

15
- Hardware Overview
  16
  - System Processors
    16
- Multiprocessor System Architecture
  16
- APIC Configuration
  17
  - Advanced Programmable Interrupt Controller
    17
  - System Memory
    18
  - I/O Expansion Bus
    18
  - BIOS Overview
    19
  - Operating System Overview
    19
Chapter 3 Hardware Specification

21
- System Memory Configuration
  21
- System Memory Cacheability and Shareability
  22
- System Memory Address Map
  22
  - External Cache Subsystem
    24
  - Locking
    24
  - MP Configuration Table
    25
  - Posted Memory Write
    25
  - Multiprocessor Interrupt Control
    25
    
    APIC Architecture
    25
    
    Interrupt Modes
    26
- APIC Versions
  26
  - PIC Mode
    27
- PIC Mode
  28
  - Virtual Wire Mode
    29
- Virtual Wire Mode Via Local APIC
  29
- Virtual Wire Mode Via I/O APIC
  30
  - Default Configurations
    31
  - Symmetric I/O Mode
    31
  - APIC Memory Mapping
    32
  - Assignment of System Interrupts to the APIC Local Unit
    32
  - Floating Point Exception Interrupt
    32
  - APIC Identification
    33
  - APIC Interval Timers
    33
  - Multiple I/O APIC Configurations
    33
  - RESET Support
    34
    
    System-Wide RESET
    34
- Multiple I/O APIC Configurations
  34
  - System-Wide INIT
    35
  - Processor-Specific INIT
    35
  - System Initial State
    36
  - Support for Fault-Resilient Booting
    36
Chapter 4 MP Configuration Table

37
Chapter 5 Default Configurations

61
Appendix A System BIOS Programming Guidelines

69
Appendix B Operating System Programming Guidelines

75
- Operating System Boot-Up
  75
- Operating System Booting and Self-Configuration
  76
- Interrupt Mode Initialization and Handling
  76
- Application Processor Startup
  77
- B-1. Universal Start-Up Algorithm
  77
  - Using Init Ipi
    78
  - Using Startup Ipi
    79
  - AP Shutdown Handling
    79
  - B.5 AP Shutdown Handling
    79
  - Other IPI Applications
    80
    
    Handling Cache Flush
    80
    
    Handling TLB Invalidation
    80
    
    Handling PTE Invalidation
    80
  - Spurious APIC Interrupts
    80
  - Supporting Unequal Processors
    81
Appendix C System Compliance Checklist

83
Appendix D Multiple I/O APIC Multiple PCI Bus Systems

85
Appendix E Errata

89
Glossary

95

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