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Intel MultiProcessor manual available for free PDF download: Specification
Intel MultiProcessor Specification (97 pages)
Intel MultiProcessor Specification
Brand:
Intel
| Category:
Computer Hardware
| Size: 0.39 MB
Table of Contents
3
Revision History
5
Table of Contents
11
Chapter 1 Introduction
11
Goals
11
Conceptual Overview
12
Features of the Specification
12
Scope
13
Target Audience
13
Organization of This Document
14
Memory Layout Conventions
14
Conventions Used in This Document
14
For More Information
15
Chapter 2 System Overview
16
Hardware Overview
16
System Processors
16
Multiprocessor System Architecture
17
APIC Configuration
17
Advanced Programmable Interrupt Controller
18
System Memory
18
I/O Expansion Bus
19
BIOS Overview
19
Operating System Overview
21
Chapter 3 Hardware Specification
21
System Memory Configuration
22
System Memory Cacheability and Shareability
22
System Memory Address Map
24
External Cache Subsystem
24
Locking
25
MP Configuration Table
25
Posted Memory Write
25
Multiprocessor Interrupt Control
25
APIC Architecture
26
Interrupt Modes
26
APIC Versions
27
PIC Mode
28
PIC Mode
29
Virtual Wire Mode
29
Virtual Wire Mode Via Local APIC
30
Virtual Wire Mode Via I/O APIC
31
Default Configurations
31
Symmetric I/O Mode
32
Assignment of System Interrupts to the APIC Local Unit
32
Floating Point Exception Interrupt
32
APIC Memory Mapping
33
APIC Identification
33
APIC Interval Timers
33
Multiple I/O APIC Configurations
34
RESET Support
34
System-Wide RESET
34
Multiple I/O APIC Configurations
35
System-Wide INIT
35
Processor-Specific INIT
36
System Initial State
36
Support for Fault-Resilient Booting
37
Chapter 4 MP Configuration Table
37
MP Configuration Data Structures
39
MP Floating Pointer Structure
41
MP Configuration Table Header
42
Base MP Configuration Table Entries
42
MP Configuration Table Header Fields
43
Processor Entries
43
Processor Entry
44
Processor Entry Fields
45
Intel486™ and Pentium ® Processor Signatures
45
Feature Flags From CPUID Instruction
46
Bus Entries
46
Bus Entry
46
Bus Type String Values
48
I/O APIC Entries
48
I/O Interrupt Assignment Entries
48
I/O APIC Entry
49
I/O Interrupt Entry
50
Interrupt Type Values
50
I/O Interrupt Entry Fields
51
Local Interrupt Assignment Entries
51
Local Interrupt Entry
52
Local Interrupt Entry Fields
53
Extended MP Configuration Table Entries
53
Extended MP Configuration Table Entry Types
54
System Address Space Mapping Entries
54
System Address Space Entry
55
System Address Space Mapping Entry Fields
57
Bus Hierarchy Descriptor Entries
58
Compatibility Bus Address Space Modifier Entries
58
Bus Hierarchy Descriptor Entry Fields
59
Compatibility Bus Address Space Modifier Entry
60
Compatibility Bus Address Space Modifier Entry Fields
60
Predefined Range Lists
61
Chapter 5 Default Configurations
62
Default Configurations
62
Discrete APIC Configurations
63
Default Configuration for Discrete APIC
64
Integrated APIC Configurations
65
Default Configuration for Integrated APIC
66
Default Configuration Interrupt Assignments
66
Assignment of I/O Interrupts to the APIC I/O Unit
67
EISA and IRQ13
67
Level-Triggered Interrupt Support
67
Assignment of System Interrupts to the APIC Local Unit
69
Appendix A System BIOS Programming Guidelines
69
BIOS Post Initialization
70
Controlling the Application Processors
70
Programming the APIC for Virtual Wire Mode
71
A-1. Programming Local APIC for Virtual Wire Mode
72
Constructing the MP Configuration Table
75
Appendix B Operating System Programming Guidelines
75
Operating System Boot-Up
76
Operating System Booting and Self-Configuration
76
Interrupt Mode Initialization and Handling
77
Application Processor Startup
77
B-1. Universal Start-Up Algorithm
78
Using Init Ipi
79
Using Startup Ipi
79
AP Shutdown Handling
79
B.5 AP Shutdown Handling
80
Other IPI Applications
80
Handling Cache Flush
80
Handling TLB Invalidation
80
Handling PTE Invalidation
80
Spurious APIC Interrupts
81
Supporting Unequal Processors
83
Appendix C System Compliance Checklist
85
Appendix D Multiple I/O APIC Multiple PCI Bus Systems
85
Interrupt Routing with Multiple Apics
85
Variable Interrupt Routing
86
Fixed Interrupt Routing
87
Bus Entries in Systems with More Than One PCI Bus
87
I/O Interrupt Assignment Entries for PCI Devices
87
D-1. I/O Interrupt Entry Source Bus IRQ Field for PCI Devices
89
Appendix E Errata
89
MP Floating Pointer Structure
90
MP Floating Pointer Structure Fields
94
Bus Hierarchy Descriptor Entry
95
Glossary
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