Intel 6300ESB ICH Manuals

Manuals and User Guides for Intel 6300ESB ICH. We have 4 Intel 6300ESB ICH manuals available for free PDF download: Datasheet, Design Manual, User Manual

Intel 6300ESB ICH Datasheet (848 pages)

I/O Controller Hub

Brand: Intel | Category: Switch | Size: 8.23 MB

Table of Contents

8
Table of Contents

17
Table of Contents

21
Table of Contents

25
- Revision History
  47
- About this Document
  49
  - Intel ® 6300ESB ich and System Clock Domains
    53
  - Conceptual System Clock Diagram
    54
  - Hub Interface Signals
    55
  - Signal Description
    55
  - Firmware Hub Interface Signals
    56
  - PCI Interface Signals
    57
  - PCI-X Interface Signals
    60
  - SATA Interface Signals
    64
  - IDE Interface Signals
    64
  - LPC Interface Signals
    66
  - Interrupt Signals
    66
- Industry Specifications
  49
3.18 Universal Asynchronous Receive and Transmit (Uart0,1)

73
- 3.17 AC'97 Link
  
  76
- 3.18 Universal Asynchronous Receive and
  
  80
  - Interrupt Interface
    66
    
    USB Interface Signals
    67
    
    Power Management Interface Signals
    68
    
    CPU Interface Signals
    69
    
    Real Time Clock Interface
    71
    
    SM Bus Interface Signals
    71
    
    System Management Interface Signals
    71
    
    Miscellaneous Signals
    72
    
    Other Clocks
    72
    
    AC'97 Link Signals
    73
    
    Universal Asynchronous Receive and Transmit (UART0,1)
    73
    
    General Purpose I/O
    74
    
    General Purpose I/O Signals
    75
    
    Name
    76
    
    Power and Ground Signals
    76
    
    Functional Strap Definitions
    77
    
    Pin Straps
    77
    
    Revision and Device ID Table
    78
    
    Intel ® 6300ESB I/O Controller Hub Power Planes
    79
    
    Intel ® 6300ESB ich Power Planes and Pin States
    79
    
    Ac_Bitclk
    80
    
    Ac_Rst
    80
    
    Ac_Sdin[2:0]
    80
    
    Ac_Sdout
    80
    
    Ac_Sync
    80
    
    Integrated Pull-Up and Pull-Down Resistors
    80
    
    Notes
    80
    
    Power Plane Usage Model
    80
    
    Table 26
    80
  - Integrated Pull-Ups and Pull-Downs
    80
    
    IDE Series Termination Resistors
    81
    
    Power Plane and States for Output and I/O Signal for Desktop Configurations
    83
    
    Signal Name
    83
  - Power Planes for Input Signals
    83
    
    Siu0_Cts
    89
    
    Siu0_Rxd
    89
    
    Siu0_Txd
    89
    
    Siu1_Cts
    89
    
    Siu1_Rxd
    89
    
    Siu1_Txd
    89
    
    Uart_Clk
    89
    
    Power Plane for Input Signals for Desktop Configurations
    90
    
    Functional Description
    91
    
    Intel Intel ® ® 6300ESB ICH-USB Port Connections
    92
    
    PCI-To-PCI Bridge Model
    92
    
    Primary Device Status Register Error Reporting Logic
    93
    
    Secondary Status Register Error Reporting Logic
    94
    
    NMI# Generation Logic
    95
    
    Parity Error Detection
    95
    
    Standard PCI Bus Configuration Mechanism
    96
    
    Type 0 Configuration Cycle Device Number Translation
    96
    
    PCI Dual Address Cycle (DAC) Support
    97
    
    LPC Cycle Types Supported
    98
    
    Start Field Bit Definitions
    98
    
    Cycle Type Bit Definitions
    99
    
    Cycle Type/Direction (CYCTYPE + DIR)
    99
    
    SYNC Bit Definition
    99
    
    Transfer Size Bit Definition
    99
    
    Response to Sync Failures
    100
    
    SYNC Time-Out
    100
    
    Abort Mechanism
    101
    
    Typical Timing for LFRAME
    101
    
    LPC Power Management
    102
  - DMA Operation (D31:F0)
    103
    
    Channel Priority
    104
    
    Fixed Priority
    104
    
    Address Shifting in 16-Bit I/O DMA Transfers
    105
    
    DMA Transfer Size
    105
    
    Summary of DMA Transfer Sizes
    105
    
    Software Commands
    106
    
    Abandoning DMA Requests
    107
    
    DMA Request Assertion through LDRQ
    107
    
    General Flow of DMA Transfers
    108
    
    SYNC Field/Ldrq# Rules
    109
  - Timers (D31:F0)
    110
    
    Counter Operating Modes
    111
    
    Reading from the Interval Timer
    111
    
    Interrupt Controller Core Connections
    113
    
    Read Back Command
    113
    
    Interrupt Handling
    114
    
    Interrupt Status Registers
    114
    
    Content of Interrupt Vector Byte
    115
    
    Initialization Command Words (Icwx)
    115
    
    Icw3
    116
    
    Modes of Operation
    117
    
    Poll Mode
    118
    
    Normal End of Interrupt
    119
    
    Port 60 Read Clearing IRQ1 and IRQ12 Latch
    120
    
    Special Handling of IRQ1 and IRQ12
    120
    
    Advanced Interrupt Controller (APIC) (D29:F5)
    121
    
    Boot Interrupt
    122
    
    Interrupt Mapping in Non-APIC
    123
    
    APIC Bus Functional Description
    124
    
    APIC Interrupt Mapping, APIC0 Agent
    124
    
    APIC Interrupt Mapping, APIC1 Agent
    125
    
    APIC Message Formats
    126
    
    Arbitration Cycles
    126
    
    EOI Message
    127
    
    Short Message
    128
    
    APIC Bus Status Cycle Definition
    129
    
    Lowest Priority Message (Without Focus Processor)
    130
    
    Remote Read Message
    131
    
    PCI Message-Based Interrupts
    132
    
    Registers and Bits Associated with PCI Interrupt Delivery
    133
    
    Interrupt Message Address Format
    134
    
    Level-Triggered Operation
    134
    
    Interrupt Message Data Format
    135
  - Serial Interrupt (D31:F0)
    135
    
    Start Frame
    136
    
    Data Frame Format
    137
    
    Stop Frame Explanation
    137
  - Real Time Clock (D31:F0)
    138
    
    Lockable RAM Ranges
    139
    
    Configuration Bits Reset by RTCRST# Assertion
    140
    
    INIT# Going Active
    141
  - Processor Interface (D31:F0)
    141
    
    Coprocessor Error Timing Diagram
    142
    
    DP Signal Differences
    143
    
    NMI Sources
    143
    
    STPCLK# and CPUSLP# Signals
    143
  - Power Management (D31:F0)
    145
    
    General Power States for Systems Using Intel 6300ESB ich
    146
    
    State Transition Rules for Intel 6300ESB I/O Controller Hub
    147
    
    System Power Plane
    148
    
    Causes of SCI
    149
    
    SMI#/SCI Generation
    149
    
    Causes of SMI
    150
    
    Causes of TCO SMI
    151
    
    Break Events
    152
    
    Dynamic Processor Clock Control
    152
    
    DS November
    153
    
    Latching Processor I/F Signals with STOPCLK
    154
    
    STPCLK# Implementation Notes
    154
  - Sleep States
    155
    
    Causes of Wake Events
    156
    
    Sleep Types
    156
    
    Sx-G3-Sx, Handling Power Failures
    157
    
    Transitions Due to Power Failure
    158
  - Thermal Management
    158
    
    THRM# Override Software Bit
    159
    
    Transitions Due to Power Button
    160
    
    PME# - PCI Power Management Event
    161
    
    Transitions Due to RI# Signal
    161
  - ALT Access Mode
    162
    
    Write Only Registers with Read Paths in ALT Access Mode
    163
    
    Programmable Interrupt Controller (PIC) Reserved Bits
    164
    
    PIC Reserved Bits Return Values
    165
    
    Read-Only Registers with Write Paths in ALT Access Mode
    165
    
    Register Write Accesses in ALT Access Mode
    165
    
    Intel ® 6300ESB ich Clock Inputs
    167
    
    Power States
    167
  - Legacy Power Management Theory of Operation
    168
  - TCO Signal Usage
    169
  - TCO Theory of Operation
    170
    
    Detecting Improper FWH Programming
    171
    
    Event Transitions that Cause Messages
    172
  - Heartbeat and Event Reporting through Smlink/Smbus
    172
    
    General Purpose I/O
    176
    
    GPIO Implementation
    176
  - Power Wells
    178
  - PIO Transfers
    179
    
    IDE Legacy I/O Ports: Command Block Registers (Cs1X# Chip Select)
    180
    
    IDE Transaction Timings (PCI Clocks)
    181
    
    PIO 32-Bit IDE Data Port Accesses
    181
    
    Bus Master Function
    182
    
    Physical Region Descriptor Table Entry
    182
    
    Error Conditions
    185
    
    Interrupt/Active Bit Interaction Definition
    185
    
    Ultra ATA/33 Protocol
    186
    
    Ultraata/33 Control Signal Redefinitions
    186
    
    Ultra ATA/66 Protocol
    188
  - SATA Host Controller (D31:F2)
    189
    
    Power State Mappings
    190
    
    SATA Power States
    190
    
    SATA Interrupts
    192
    
    SATA MSI Vs. PCI IRQ Actions
    192
    
    Legacy Routing
    193
    
    Timer Accuracy
    193
    
    Enabling the Timers
    195
    
    Frame List Pointer Bit Description
    196
  - USB UHCI Controllers (D29:F0 and F1)
    196
    
    Transfer Descriptor
    197
    
    TD Control and Status
    198
    
    TD Token
    200
    
    Queue Element Link Pointer
    201
    
    Queue Head Block
    201
    
    Queue Head Link Pointer
    201
    
    TD Buffer Pointer
    201
    
    Data Transfers To/From Main Memory
    202
    
    Command Register, Status Register and TD Status Bit Interaction
    204
    
    Example Queue Conditions
    205
    
    TD Link Pointer
    205
    
    Queue Advance Criteria
    206
    
    USB Schedule List Traversal Decision Table
    207
    
    Data Encoding and Bit Stuffing
    208
    
    USB Data Encoding
    208
    
    PID Format
    209
    
    Address Field
    210
    
    PID Types
    210
    
    Endpoint Field
    211
    
    Packet Formats
    211
    
    SOF Packet
    212
    
    Token Format
    212
    
    Handshake Responses
    213
    
    USB Interrupts
    214
    
    USB Power Management
    216
    
    USB Legacy Keyboard/Mouse Control Register Bit Implementation
    217
    
    USB Legacy Keyboard Flow Diagram
    219
    
    USB Legacy Keyboard State Transitions
    220
    
    UHCI Vs. EHCI
    221
  - USB EHCI Controller (D29:F7)
    221
    
    5.18.2.4 EHC Resets
    222
    
    Power on
    222
    
    Data Structures in Main Memory
    223
    
    5.18.4.1.1 Read Policies for Periodic DMA
    224
    
    USB 2.0 Enhanced Host Controller DMA
    224
    
    5.18.4.1.2 Write Policies for Periodic DMA
    225
    
    5.18.4.2.1 Read Policies for Asynchronous DMA
    226
    
    Data Encoding and Bit Stuffing
    227
    
    Write Policies for Asynchronous DMA
    227
    
    Aborts on USB EHCI-Initiated Memory Reads
    228
    
    Interaction with Classic Host Controllers
    230
    
    Device Connects
    231
    
    5.18.9.4 Effect of Resets on Port-Routing Logic
    232
    
    USB 2.0 Legacy Keyboard Operation
    232
    
    USB Debug Port Behavior
    233

intel 6300ESB ICH Design Manual (320 pages)

Chipset, ICH Embedded Platform

Brand: intel | Category: Computer Hardware | Size: 4.92 MB

Intel 6300ESB ICH User Manual (38 pages)

Processor with 800 MHz System Bus, Chipset and Development Kit

Brand: Intel | Category: Computer Hardware | Size: 1.22 MB

Table of Contents
3
Intel ® Xeon™ Processor, Intel
4
Revision History
6
1 Product Overview

7
- Related Documents
  7
- Product Contents
  7
- Products Feature List
  8
- Block Diagram
  9
  - 6300ESB Customer Reference Board Block Diagram
    9
  - E7520 and Intel
    9
  - Placement - Top View
    10
  - DIMM Placement DDR2 400
    11
  - Memory Subsystem
    11
  - Supported DIMM Module Types
    11
- Memory Population Rules and Configurations
  12
- DDR2 400 Memory - DIMM Ordering
  12
2 Platform Management

13
- Power Button
  13
- Soft off
  13
- Sleep States Supported
  13
  - S0 State
    13
  - S1 State
    14
  - S2 State
    14
  - S3 State
    14
  - S4 State
    14
  - S5 State
    15
  - Wake-Up Events
    15
  - Wake-Up from S1 Sleep State
    15
  - Wake-Up from S4 and S5 States
    15
- PCI PM Support
  15
- Platform Management
  15
  - Processor Thermal Management
    16
- System Fan Operation
  16
3 Equipment Required for CRB Usage

17
- Precautions
  17
- Driver and os Requirements
  18
  - Drivers Included on CD
    18
4 Jumpers and Headers

21
5 System Overview

25
- Power Diagrams
  25
- Power Distribution Block Diagram
  25
- Platform Clocking
  26
- Clock Block Diagram
  26
- Platform Resets
  27
- Platform Reset Diagram
  27
- Smbus
  28
- Smbus Block Diagram
  28
- Platform IRQ Routing
  29
- IRQ Routing Diagram
  29
- VRD VID Headers
  30
- Processor VRD Settings
  30
- Miscellaneous Buttons
  32
- Power Buttons
  32

Intel 6300ESB ICH Design Manual (14 pages)

I/O Controller Hub Thermal and Mechanical Design Guide

Brand: Intel | Category: Switch | Size: 0.19 MB

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