80386 Bus States Timing Example - Intel 80386 Reference Manual

CLK2 [
(82384 CLK) [
BED #-BEI
#
A2-A31, [
M/IO#,O/C#
W/R# [
A05# [
NAN [
B516
# [
READY# [
LOCK # [
00- D31 [
LOCAL BUS INTERFACE
IDLE
I
CYCLE 1
I
NON-PIPELINED
(READ)
CYCLE 2
NON-PIPELINED
(WRITE)
TI
T1
T2
T1 T2 T2
-nn nn
1Il
nn
lJl
nn
-V V
\ J \ J \ J \ J
TI
nn
\ J
T1
CYCLE 3
NON-PIPELINED
(READ)
T2 T2
rLJ1.
nn nn
\ f
V V
TI
nn
V
XIXXXXIX
VALID I
X
VALID 2
XXXXX
VALID
3
IXXXX
IXXX I),
/
,(XXX)'
tx'XX
" -
; -
'--I
I'-- /
XXXXX
XXXX XXXX XXXX(f
'(,XXXX XXX XXX 1 '<XXXX XXXX
32-BIT 32-BIT
32-BIT
BUS lSIZE
BUS
1
SIZE
BU\SIZE
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'<
XX XX IY
'<
XX IXXX)( XXXXY '<~
XXXXX XXXX Xx\' /'xX IXXY
~ ~XX IXXXX XXY ~
J.' X ' X
END CYCLE I
END CYCLE 2 END CYCLE
3
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VALID I
OC
VALID 2
IXXX
VALID
3
IXXXX
-----~--¢< --¢---
.
-----
OUT
--
-- --- --
._---
I
Idle slales are shown here for diagram variety only. Wrile cycles are not always followed by an idle slale. An aclive bus cycle can immedialely
follow Ihe wrile cycle.
231630-16
Figure 3-2. 80386 Bus States Timing Example
The programmer views the address space (memory or I/O) of the 80386 as a sequence of
bytes_ Words consist of two consecutive bytes, and double words consist of four consecutive
bytes_ However, in the system hardware, address space is implemented in four sections. Each
of the four 8-bit portions of the data bus (DO-D7, D8-D15, D16-D23, and D24-D31) connects
to a section. When the 80386 reads a doubleword, it accesses one byte from each section.
The 80386 automatically translates the programmers' view of consecutive bytes into this
hardware implementation (see Figure 3-5).
The 80386 memory spaces and I/O space are organized physically as sequences of 32-bit
doublewords (2
30
32-bit memory locations and 214 32-bit I/O ports maximum). Each double-
word starts at a physical address that is a multiple of four, and has four individually address-
able bytes at consecutive addresses.
3-6