4.3.13 Bus States - Intel Embedded Intel486 Hardware Reference Manual

AHOLD is asserted, and in the second clock BOFF# is asserted. This guarantees that ADS# is
not floating low. This is necessary only in systems where BOFF# may be asserted in the same
clock as ADS#.

4.3.13 Bus States

A bus state diagram is shown in
given in Table 4-10.
(RDY# Asserted + (BRDY# · BLAST#) Asserted) ·
(HOLD + AHOLD + No Request) · BOFF# Deasserted
Ti
†
HOLD is only factored into this state transition if T
entered while a non-cacheable. non-burst, code prefetch was
in progress. Otherwise, ignore HOLD.
Figure 4-35. A description of the signals used in the diagram is
Request Pending · (RDY# Asserted +
(BRDY# · BLAST#) Asserted) ·
HOLD Deasserted · AHOLD Deasserted · BOFF# Deasserted
Request Pending ·
HOLD Deasserted ·
T1
AHOLD Deasserted ·
BOFF# Deasserted
BOFF#
Asserted
T
b
b
Figure 4-35. Bus State Diagram
BOFF# Deasserted
BOFF# Asserted
AHOLD Deasserted ·
BOFF# Deasserted ·
†
(HOLD) Deasserted
was
BUS OPERATION
T2
BOFF#
Deasserted
T1b
240950–069
4-45