Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus - Intel 80960HA Datasheet

Figure 36. Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus
PMCON
A31:4, SUP,
CT3:0, D/C,
BE3:0, LOCK
Datasheet
External
Pipe-
Function Ready
Burst
Lining
Control
Bit
28 24
29
OFF
Enabled
Disabled
Value
0
1
0
NOTE:
Bits 31-30, 27-25, 13, and 5 are reserved.
A 2
CLKIN
ADS
W/R
BLAST
DT/R
DEN
A3:2
WAIT
D31:0,
DP3:0
PCHK
Parity
Bus
Odd
N
Parity Enable XDA
Width
23-22 21 20 19-16
X Enabled
32-Bit 1
x 1
10 0001
1 D 1 D 1
Valid
00 01
In0 In1
80960HA/HD/HT
N
N
N N
RAD
WDD WAD RDD
15-14 12-8 7-6 4-0
X X
1 2
xx xxxxx
01 00010
D 1 D 1 A
10 11
In2 In3
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