Default Peg/Dmi Vtd Remapping Engine Registers; Default Peg/Dmi Vtd Remapping Engine Register Address Map - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.21 Default PEG/DMI VTd Remapping Engine
Registers
Table 2-23
the sections following the table.
Table 2-23. Default PEG/DMI VTd Remapping Engine Register Address Map (Sheet 1 of 2)
Address
Offset
0–3h
4–7h
8–Fh
10–17h
18–1Bh
1C–1Fh
20–27h
28–2Fh
30–33h
34–37h
38–3Bh
3C–3Fh
40–43h
44–47h
48–57h
58–5Fh
60–63h
64–67h
68–6Bh
6C–6Fh
70–77h
78–7Fh
80–87h
88–8Fh
90–97h
98–9Bh
9C–9Fh
A0–A3h
A4–A7h
Datasheet, Volume 2
lists the registers arranged by address offset. Register bit descriptions are in
Register
Symbol
VER_REG Version Register
RSVD Reserved
Capability Register
CAP_REG
Extended Capability Register
ECAP_REG
GCMD_REG Global Command Register
GSTS_REG Global Status Register
Root-Entry Table Address Register
RTADDR_REG
Context Command Register
CCMD_REG
RSVD Reserved
Fault Status Register
FSTS_REG
FECTL_REG Fault Event Control Register
FEDATA_REG Fault Event Data Register
FEADDR_REG Fault Event Address Register
FEUADDR_REG Fault Event Upper Address Register
RSVD Reserved
Advanced Fault Log Register
AFLOG_REG
RSVD Reserved
PMEN_REG Protected Memory Enable Register
PLMBASE_REG Protected Low-Memory Base Register
PLMLIMIT_REG Protected Low-Memory Limit Register
Protected High-Memory Base Register
PHMBASE_REG
Protected High-Memory Limit Register
PHMLIMIT_REG
Invalidation Queue Head Register
IQH_REG
Invalidation Queue Tail Register
IQT_REG
Invalidation Queue Address Register
IQA_REG
RSVD Reserved
ICS_REG Invalidation Completion Status Register
IECTL_REG Invalidation Event Control Register
IEDATA_REG Invalidation Event Data Register
Register Name Reset Value Access
00000010h RO
0h RO
00C9008020
RO
660262h
0000000000
RO-V, RO
F010DAh
00000000h WO, RO
00000000h RO, RO-V
0000000000
RW
000000h
0000000000 RW-V, RW,
000000h RO-V
0h RO
RW1CS, ROS-
00000000h
V, R O
80000000h RW, RO-V
00000000h RW
00000000h RW
00000000h RW
0h RO
0000000000
RO
000000h
0h RO
00000000h RW, RO-V
00000000h RW
00000000h RW
0000000000
RW
000000h
0000000000
RW
000000h
0000000000
RO-V
000000h
0000000000
RW-L
000000h
0000000000
RW-L
000000h
0h RO
00000000h RW1CS
80000000h RW-L, RO-V
00000000h RW-L
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