Register Attributes; Reserved Bits Defined In Registers; Reserved Or Undefined Register Locations; Default Upon Reset - Intel 460GX Software Developer’s Manual

translates CF8/CFC accesses to the MAC registers into read/write commands over the I2C port.
The SAC also contains an IIADR pointer register that can be used in conjunction with a CF8/CFC
access to generate I2C commands to generic I2C devices on the memory boards.
2.2.2

Register Attributes

Registers have designated "access attributes", with the following definitions:
Read Only
Read/Write
Read/Clear
Sticky
2.2.3

Reserved Bits Defined in Registers

Most 460GX chipset registers described in this section contain reserved bits. The PCI specification
requires that software correctly handle reserved fields, as follows. On reads, software must use
appropriate masks to extract the defined bits and not rely on reserved bits being any particular
value. On writes, software must ensure that the values of reserved bit positions are preserved. That
is, the values of reserved bit positions must first be read, merged with the new values for other bit
positions and then written back. Note the software does not need to perform read, merge, write
operation for the CONFIG_ADDRESS register.
2.2.4

Reserved or Undefined Register Locations

In addition to reserved bits within a register, the 460GX chipset contains address locations in the
PCI configuration space that are marked "Reserved" or are simply undefined. Several of the
460GX chipset devices are multi-function devices; all registers in the unused functions are
considered "Reserved". Reserved registers can be 8-, 16-, or 32-bit in size. The PCI specification
requires that the 460GX chipset respond to accesses to these address locations by completing the
host cycle. Reserved register locations must be treated by software the same as reserved fields are
treated: software can not rely on reads returning any particular value, and must not attempt to
change the value returned when read.
2.2.5

Default Upon Reset

Upon reset, the 460GX chipset sets its internal configuration registers to predetermined default
states. The default state represents the minimum functionality feature set required to successfully
bring up the system. Hence, it does not represent the optimal system configuration. It is the
responsibility of the system initialization software (firmware) to properly determine the DRAM
configurations, operating parameters and optional system features that are applicable, and to
program the 460GX chipset registers accordingly.
Intel® 460GX Chipset Software Developer's Manual
Writes to this register have no effect.
Data may be read from and written to this register. Selected bits in the register may
be designated as "hardwired" or "read-only"; such bits are not affected by data writes
to the register.
Data may be read from the register. A data write operates strictly as a clear: a "1"-bit
in the data field clears the corresponding bit in the register, while a "0"-bit in the data
field has no effect on the corresponding bit in the register. Selected bits in the register
may be designated as "hardwired" or "read-only"; such bits are not affected by data
writes to the register.
Data in this register remains valid and unchanged, during and following a hard reset.
Typically, these registers contain special configuration information or error logs.
Register Descriptions
2-3