Processor Reset# Signal; Trace Spacing Vs. Trace Width Example; Processor Reset# Signal Routing Topology With No Itp700Flex Connector - Intel Pentium M Processor Design Manual

® ®
Intel Pentium M Processor and Intel
System Bus Routing Guidelines
Figure 24.

Trace Spacing vs. Trace Width Example

5.1.4.2

Processor RESET# Signal

The RESET# signal is a common clock signal driven by the MCH CPURESET# pin. In a
production system where no ITP700FLEX debug port is implemented, a simple point-to-point
connection between the CPURESET# pin of the MCH and Intel
RESET# pin is recommended. On-die termination of the AGTL+ buffers on both the processor and
the MCH provide proper signal quality for this connection. This is the same case as for the other
common clock signals listed in
guidelines given for common clock signals listed in
Figure 25.

Processor RESET# Signal Routing Topology With NO ITP700FLEX Connector

For a system that implements an ITP700FLEX debug port a more elaborate topology is required in
order to ensure proper signal quality at both the processor signal pad and the ITP700FLEX input
receiver. In this case the topology illustrated in
implemented.
The CPURESET# signal from the MCH should fork out (do not route one trace from MCH pin and
then T-split) towards the processor's RESET# pin as well as towards the R
termination network placed next to the ITP700FLEX debug port connector. R
VCCP voltage and is placed at the end of the L2 line. R
minimize the routing between them in the vicinity of the ITP700FLEX connector to limit the L3
length. ITP700FLEX operation requires the matching of L2 + L3 - L1 length to the length of the
BPM[4:0]# signals length within ± 50 ps.
Currently 1% tolerance resistors are recommended for R
for these resistors and whether it could provide adequate signal quality performance is under
investigation.
60
®
E7501 Chipset Platform
T ra c e
Section 5.1.6, "Common Clock
CPU
3 X
®
Pentium
Signals". Follow the same routing
Section 5.1.6.
MCH
L1
Figure 26 and listed in Table 16
should be placed right next to R
S
and R . The use of 5% tolerant resistors
tt
S
T ra c e
X
®
M processor's
B0054-01
should be
and R resistive
tt
S
pulls-up to the
tt
to
tt
Design Guide