Bsp Register Format; Bspstore Register Format; Rnat Register Format - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

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Figure 3-4.
63
3.1.8.4
RSE Backing Store Pointer for Memory Stores (BSPSTORE – AR 18)
The RSE Backing Store Pointer for memory stores is a 64-bit register
holds the address of the location in memory to which the RSE will spill the next value.
See
Section 6.1, "RSE and Backing Store Overview" on page
Figure 3-5.
63
3.1.8.5
RSE NaT Collection Register (RNAT – AR 19)
The RSE NaT Collection Register is a 64-bit register
temporarily hold NaT bits when it is spilling general registers. Bit 63 always reads as
zero and ignores all writes. See
page
2:133.
Figure 3-6.
63
ig
1
3.1.8.6
Compare and Store Data register (CSD – AR 25)
The Compare and Store Data register is a 64-bit register that provides data to be
stored by the Itanium st16 and cmp8xchg16 instructions, and receives data loaded by
the Itanium ld16 instruction.
For implementations that do not support the ld16, st16 and cmp8xchg16 instructions,
bits 61:60 may be optionally implemented. This means that on move application
register instructions the implementation can either ignore writes and return zero on
reads, or write the value and return the last value written on reads. For
implementations that do support the ld16, st16 and cmp8xchg16 instructions, all bits of
CSD are implemented.
For IA-32 execution, this register is the IA-32 Code Segment Descriptor. See
Section 6.2.2.3, "IA-32 Segment Registers" on page
3.1.8.7
Compare and Exchange Value Register (CCV – AR 32)
The Compare and Exchange Value Register is a 64-bit register that contains the
compare value used as the third source operand in the Itanium cmpxchg instruction.
1:30

BSP Register Format

pointer

BSPSTORE Register Format

pointer
Section 6.1, "RSE and Backing Store Overview" on

RNAT Register Format

RSE NaT Collection
61
61
(Figure
3-6) used by the RSE to
63
1:118.
Volume 1, Part 1: Execution Environment
3
2
1
0
3
(Figure
3-5). It
2:133.
3
2
1
ig
3
0
0
0

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