Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 42

3.1.8.8 User NaT Collection Register (UNAT – AR 36)
The User NaT Collection Register is a 64-bit register used to temporarily hold NaT bits
when saving and restoring general registers with the ld8.fill and st8.spill
instructions.
3.1.8.9 Floating-point Status Register (FPSR – AR 40)
The floating-point status register (FPSR) controls traps, rounding mode, precision
control, flags, and other control bits for Itanium floating-point instructions. FPSR does
not control or reflect the status of IA-32 floating-point instructions. For more details on
the FPSR, see
3.1.8.10 Interval Time Counter (ITC – AR 44)
The Interval Time Counter (ITC) is a 64-bit register which counts up at a fixed
relationship to the input clock to the processor. The ITC may be clocked at a somewhat
lower frequency than the instruction execution frequency. This clocking relationship is
described in the PAL procedure PAL_FREQ_RATIOS on
guaranteed to be clocked at a constant rate, even if the instruction execution frequency
may vary.
A sequence of reads of the ITC is guaranteed to return ever-increasing values (except
for the case of the counter wrapping back to 0) corresponding to the program order of
the reads. Applications can directly sample the ITC for time-based calculations.
System software can secure the interval time counter from non-privileged access.
When secured, a read of the ITC at any privilege level other than the most privileged
causes a Privileged Register fault. The ITC can be written only at the most privileged
level. The IA-32 Time Stamp Counter (TSC) is similar to ITC counter. ITC can directly be
read by the IA-32 rdtsc (read time stamp counter) instruction. System software can
secure the ITC from non-privileged IA-32 access. When secured, an IA-32 read of the
ITC at any privilege level other than the most privileged raises an
IA_32_Exception(GPfault).
3.1.8.11 Resource Utilization Counter (RUC – AR 45)
The Resource Utilization Counter (RUC) is a 64-bit register which counts up at a fixed
relationship to the input clock to the processor, when the processor is active. RUC
provides an estimate of the portion of resources used by a logical processor with
respect to all resources provided by the underlying physical processor.
The Resource Utilization Counter (RUC) is a 64-bit register which provides an estimate
of the portion of resources used by a logical processor with respect to all resources
provided by the underlying physical processor.
In a given time interval, the difference in the RUC values for all of the logical processors
on a given physical processor add up to the difference seen in the ITC on that physical
processor for that same interval.
A sequence of reads of the RUC is guaranteed to return ever-increasing values (except
for the case of the counter wrapping back to 0) corresponding to the program order of
the reads.
Volume 1, Part 1: Execution Environment
"Floating-point Status Register" on page 1:88.
page 2:392. The ITC is
1:31