Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 50

Table 3-10.
Template
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
a. The MLX template was formerly called MLI, and for
compatibility, the X slot may encode break.i and nop.i
in addition to any X-unit instruction.
Extended instructions, used for long immediate integer and long branch instructions,
occupy two instruction slots. Depending on the major opcode, extended instructions
execute on a B-unit (long branch/call) or an I-unit (all other L+X instructions).
3.4 Instruction Sequencing Considerations
Itanium architecture-based code consists of a sequence of instructions and stops
packed in bundles. Instruction execution is ordered as follows:
• Bundles are ordered from lowest to highest memory address. Instructions in
bundles with lower memory addresses are considered to precede instructions in
bundles with higher memory addresses. The byte order of each bundle in memory
is little-endian (the template field is contained in byte 0 of a bundle).
• Within a bundle, instructions are ordered from instruction slot 0 to instruction slot 2
as specified in
Instruction execution consists of four phases:
1. Read the instruction from memory (fetch)
2. Read architectural state, if necessary (read)
3. Perform the specified operation (execute)
Volume 1, Part 1: Execution Environment
Template Field Encoding and Instruction Slot Mapping
Slot 0 Slot 1
M-unit M-unit
M-unit F-unit
M-unit F-unit
M-unit M-unit
M-unit M-unit
M-unit I-unit
M-unit I-unit
M-unit B-unit
M-unit B-unit
B-unit B-unit
B-unit B-unit
M-unit M-unit
M-unit M-unit
M-unit F-unit
M-unit F-unit
Figure 3-15 on page
Slot 2
I-unit
I-unit
I-unit
F-unit
F-unit
B-unit
B-unit
B-unit
B-unit
B-unit
B-unit
B-unit
B-unit
B-unit
B-unit
1:38.
1:39