Cpuid Register 4 - General Features/Capability Bits; Cpuid Register 3 Fields; Cpuid Register 4 Fields - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

Table 3-7.
Field
number
revision
model
family
archrev
rv
CPUID register 4 provides general application-level information about processor
features. As shown in
feature is supported in the processor model. When a bit is one the feature is supported;
when 0 the feature is not supported. The defined feature bits in the current architecture
are listed in
models the presence (or removal) of new features will be indicated by new feature bits.
CPUID register 4 is logically split into two halves, both of which contain general feature
and capability information but which have different usage models and access
capabilities; this information reflects the status of any enabled or disabled features.
Both the upper and lower halves of CPUID register 4 are accessible through the move
indirect register instruction; depending on the implementation, the latency for this
access can be long and this access method is not appropriate for low-latency code
versioning using self-selection. In addition, the upper half of CPUID register 4 is also
accessible using the test feature instruction; the latency for this access is comparable
to that of the test bit instruction and this access method enables low-latency code
versioning using self selection.
This register does not contain IA-32 instruction set features. IA-32 instruction set
features can be acquired by the IA-32 cpuid instruction.
Figure 3-12.
63
Table 3-8.
Field
lb
sd
ao
ru
rv
cz
Volume 1, Part 1: Execution Environment

CPUID Register 3 Fields

Bits
7:0 The index of the largest implemented CPUID register (one less than the number of
implemented CPUID registers). This value will be at least 4.
15:8 Processor revision number. An 8-bit value that represents the revision or stepping
of this processor implementation within the processor model.
23:16 Processor model number. A unique 8-bit value representing the processor model
within the processor family.
31:24 Processor family number. A unique 8-bit value representing the processor family.
39:32 Architecture revision. An 8-bit value that represents the architecture revision
number that the processor implements.
63:40 Reserved.
Figure 3-12, it is a set of flag bits used to indicate if a given
Table 3-8. As new features are added (or removed) from future processor
CPUID Register 4 – General Features/Capability Bits
rv
30

CPUID Register 4 Fields

Bits
0 Processor implements the long branch (brl) instructions.
1 Processor implements spontaneous deferral (see
Speculative Load Faults" on page
2 Processor implements 16-byte atomic operations (see
"cmpxchg — Compare and Exchange"
3 Processor implements the Resource Utilization Counter (AR 45).
31:4 Reserved.
32 Processor implements the clz instruction (see
Volume 3).
Description
34 33 32 31
x2 cz
1 1
Description
2:105).
instructions in
"tf — Test Feature"
4 3 2
rv ru ao sd lb
28 1 1
Section 5.5.5, "Deferral of
"ld — Load", "st — Store"
Volume 3).
instruction in
1 0
1 1
and
1:35