Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 54

br.ia work like other instructions for the purposes of register dependency; i.e., if their
qualifying predicate is 0, they are not considered readers or writers of other resources.
Branches br.cloop, br.cexit, br.ctop, br.wexit, and br.wtop are exceptional in
that they are always readers or writers of their resources, regardless of the value of
their qualifying predicate. An indirect brp is considered a reader of the specified BR.
The ld8.fill and st8.spill instructions implicitly access the User NaT Collection
application register (UNAT). For these instructions the restriction on dynamic RAW
register dependencies with respect to UNAT applies at the bit level. These instructions
may appear in the same instruction group provided they do not access the same bit of
UNAT. RAW UNAT dependencies between ld8.fill or st8.spill instructions and mov
ar= or mov =ar instructions accessing UNAT must not occur within the same instruction
group.
For the purposes of resource dependencies, CFM is treated as a single resource.
3.4.2 WAW Dependency Special Cases
There are three special cases in which WAW register dependencies within an instruction
group are permitted. The special cases are compare-type instructions, floating-point
instructions, and the st8.spill instruction.
The set of compare-type instructions includes: cmp, cmp4, tbit, tnat, tf, fcmp,
frsqrta, frcpa, and fclass. Compare-type instructions in the same instruction group
may target the same predicate register provided:
• The compare-type instructions are either all AND-type compares or all OR-type
compares (AND-type compares correspond to ".and" and ".andcm" completers;
OR-type compares correspond to ".or" and ".orcm" completers), or
• The compare-type instructions all target PR0. All WAW dependencies for PR0 are
allowed; the compares can be of any types and can be of differing types.
All other WAW dependencies within an instruction group are disallowed, including WAW
register dependencies with move to PR instructions that access the same predicate
registers as another writer.
Note: The move to PR instructions only writes those PRs indicated by its mask, but
the move from PR instructions always reads all the predicate registers.
Floating-point instructions implicitly write the Floating-point Status Register (FPSR) and
the Processor Status Register (PSR). Multiple floating-point instructions may appear in
the same instruction group since the restriction on WAW register dependencies with
respect to the FPSR and PSR do not apply. The state of FPSR and PSR after executing
the instruction group will be the logical OR of all writes.
The st8.spill instruction implicitly writes the UNAT register. For this instruction the
restriction on WAW register dependencies with respect to UNAT applies at the bit level.
Multiple st8.spill instructions may appear in the same instruction group provided
they do not write the same bit of UNAT. WAW register dependencies between
st8.spill instructions and mov ar= instructions targeting UNAT must not occur within
the same instruction group.
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