Data Speculation; Predication - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

the compiler uses control speculation, it leaves a check operation at the original
location. The check verifies whether an exception has occurred and if so it branches to
recovery code. The code sequence above now translates into:
/* off critical path */
sload(ld_addr1,target1)
sload(ld_addr2,target2)
/* other operations including uses of target1/target2 */
if (a>b) scheck(target1,recovery_addr1)
else scheck(target2, recovery_addr2)
2.6.2

Data Speculation

Data speculation is the execution of a memory load prior to a store that preceded it and
that may potentially alias with it. Data speculative loads are also referred to as
"advanced loads." Consider the code sequence below:
store(st_addr,data)
load(ld_addr,target)
use(target)
The process of determining at compile time the relationship between memory
addresses is called disambiguation. In the example above, if ld_addr and st_addr
cannot be disambiguated, and if the load were to be performed prior to the store, then
the load would be data speculative with respect to the store. If memory addresses
overlap during execution, a data-speculative load issued before the store might return a
different value than a regular load issued after the store. Therefore analogous to
control speculation, when the compiler data speculates a load, it leaves a check
instruction at the original location of the load. The check verifies whether an overlap
has occurred and if so it branches to recovery code. The code sequence above now
translates into:
/* off critical path */
aload(ld_addr,target)
/* other operations including uses of target */
store(st_addr,data)
acheck(target,recovery_addr)
use(target)
2.6.3

Predication

Predication is the conditional execution of instructions. Conditional execution is
implemented through branches in traditional architectures. The Itanium architecture
implements this function through the use of predicated instructions. Predication
removes branches used for conditional execution resulting in larger basic blocks and the
elimination of associated mispredict penalties.
To illustrate, an unpredicated instruction
r1 = r2 + r3
when predicated, would be of the form
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