Dac Channel1 12-Bit Left Aligned Data Holding Register; (Dac_Dhr12L1); Dac Channel1 8-Bit Right Aligned Data Holding Register (Dac_Dhr8R1); Dual Dac 12-Bit Right-Aligned Data Holding Register (Dac_Dhr12Rd) - ST STM32WL5 Series Reference Manual
Advanced arm-based 32-bit mcus with sub-ghz radio solution
Table of Contents
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RM0453
19.7.4
DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software.
They specify 12-bit data for DAC channel1.
Bits 3:0 Reserved, must be kept at reset value.
19.7.5
DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software. They specify 8-bit data for DAC channel1.
19.7.6
Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
27
26
25
Res.
Res.
Res.
11
10
9
DACC1DHR[11:0]
rw
rw
rw
rw
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
27
26
25
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
rw
rw
rw
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
rw
rw
24
23
22
Res.
Res.
Res.
Res.
RM0453 Rev 1
Digital-to-analog converter (DAC)
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
rw
rw
21
20
19
18
Res.
Res.
Res.
5
4
3
2
DACC1DHR[7:0]
rw
rw
rw
rw
21
20
19
18
Res.
Res.
Res.
17
16
Res.
Res.
1
0
Res.
Res.
17
16
Res.
Res.
1
0
rw
rw
17
16
Res.
Res.
611/1461
618
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