Dac Functional Description; Dac Channel Enable; Dac Output Buffer Enable; Dac Data Format - ST STM32F40 Series Reference Manual

RM0090
12.3

DAC functional description

12.3.1

DAC channel enable

Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR
register. The DAC channel is then enabled after a startup time t
Note: The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital
interface is enabled even if the ENx bit is reset.
12.3.2

DAC output buffer enable

The DAC integrates two output buffers that can be used to reduce the output impedance,
and to drive external loads directly without having to add an external operational amplifier.
Each DAC channel output buffer can be enabled and disabled using the corresponding
BOFFx bit in the DAC_CR register.
12.3.3

DAC data format

Depending on the selected configuration mode, the data have to be written into the specified
register as described below:
●
Single DAC channelx, there are three possibilities:
–
–
–
Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and
stored into the corresponding DHRx (data holding registerx, which are internal non-
memory-mapped registers). The DHRx register is then loaded into the DORx register either
automatically, by software trigger or by an external event trigger.

Figure 55. Data registers in single DAC channel mode

8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0]
bits (stored into the DHRx[11:4] bits)
12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4]
bits (stored into the DHRx[11:0] bits)
12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0]
bits (stored into the DHRx[11:0] bits)
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Doc ID 018909 Rev 4
24 15 7
Digital-to-analog converter (DAC)
.
WAKEUP
0
8-bit right aligned
12-bit left aligned
12-bit right aligned
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