Direct Memory Access Controller (Dma); Table 32. Dma_Sm_0; Table 33. Dma_Sm_1 - ST STM32F2 Series User Manual

3.6.6

Direct memory access controller (DMA)

SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known limitations Refer to NVIC_SM_0
SM CODE
Description
Ownership
Detailed implementation
Error reporting
Fault detection time
Addressed fault model
Dependency on MCU configuration
Initialization
Periodicity
Test for the diagnostic
Multiple faults protection
Recommendations and known
limitations
UM1845 - Rev 4
Table 32. DMA_SM_0
DMA_SM_0
Periodical read-back of configuration registers
End user
This method must be applied to DMA configuration register and channel addresses register as well.
Detailed information on the implementation of this method can be found in
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Refer to NVIC_SM_0
Table 33. DMA_SM_1
DMA_SM_1
Information redundancy on data packet transferred via DMA
End user
This method is implemented adding to data packets transferred by DMA a redundancy check (like a
CRC check, or similar one) with encoding capability. Full data packet redundancy would be
overkilling.
The checksum encoding capability must be robust enough to guarantee at least 90% probability of
detection for a single bit flip in the data packet
Consistency of data packet must be checked by the application software before consuming data
Depends on implementation
Depends on implementation
Permanent and Transient
None
Depends on implementation
On demand
Not needed
CPU_SM_0: periodical core self-test software
To give an example about checksum encoding capability, using just a bit-by-bit addition is
unappropriated
Description of hardware and software diagnostics
Section 3.6.5
UM1845
page 29/108