Direct Memory Access Controller (Dma); Dma Introduction; Dma Main Features - ST STM32F100 Series Reference Manual

Direct memory access controller (DMA)

9 Direct memory access controller (DMA)
Low-density value line devices are STM32F100xx microcontrollers where the flash
memory density ranges between 16 and 32 Kbytes.
Medium-density value line devices are STM32F100xx microcontrollers where the flash
memory density ranges between 64 and 128 Kbytes.
High-density value line devices are STM32F100xx microcontrollers where the flash
memory density ranges between 256 and 512 Kbytes.
This section applies to the whole STM32F100xx family, unless otherwise specified.
9.1

DMA introduction

Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory as well as memory to memory. Data can be quickly moved by DMA
without any CPU actions. This keeps CPU resources free for other operations.
The two DMA controllers have 12 channels in total (7 for DMA1 and 5 for DMA2), each
dedicated to managing memory access requests from one or more peripherals. It has an
arbiter for handling the priority between DMA requests.
9.2

DMA main features

•
12 independently configurable channels (requests): 7 for DMA1 and 5 for DMA2
•
Each of the 12 channels is connected to dedicated hardware DMA requests, software
trigger is also supported on each channel. This configuration is done by software.
• Priorities between requests from channels of one DMA are software programmable (4
levels consisting of very high, high, medium, low) or hardware in case of equality
(request 1 has priority over request 2, etc.)
•
Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
•
Support for circular buffer management
•
3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)
logically ORed together in a single interrupt request for each channel
• Memory-to-memory transfer
•
Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers
•
Access to flash, SRAM, APB1, APB2 and AHB peripherals as source and destination
•
Programmable number of data to be transferred: up to 65536
The block diagram is shown in
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Figure 20 and Figure
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21.
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