Rcc Pll Configuration Register (Rcc_Pllcfgr) - ST STM32F446 Series Reference Manual

RM0390
6.3.2

RCC PLL configuration register (RCC_PLLCFGR)

Address offset: 0x04
Reset value: 0x2400 3010
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLL clock outputs according to the formulas:
•
f
(VCO clock)
•
f
(PLL general clock output)
•
f
(USB OTG FS, SDIO)
31 30 29
Res. PLLR[2:0]
rw rw
15 14 13
Res.
rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 PLLR[2:0]: Main PLL division factor for I2Ss, SAIs, SYSTEM and SPDIF-Rx clocks
Bits 27:24 PLLQ[3:0]: Main PLL (PLL) division factor for USB OTG FS, SDIOclocks
Caution: The USB OTG FS requires a 48 MHz clock to work correctly. The SDIOneeds a
Bit 23 Reserved, must be kept at reset value.
Bit 22 PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
= f
(PLL clock input)
= f
(VCO clock)
= f
(VCO clock)
28 27 26 25
PLLQ[3:0]
rw rw rw rw
12 11 10 9
PLLN[8:0]
rw rw rw rw
Set and cleared by software to control the frequency of the clock. These bits should be
written only if PLL is disabled.
Clock frequency = VCO frequency / PLLR with 2 ≤ PLLR ≤ 7
000: PLLR = 0, wrong configuration
001: PLLR = 1, wrong configuration
010: PLLR = 2
011: PLLR = 3
...
111: PLLR = 7
Set and cleared by software to control the frequency of USB OTG FS clock and the
SDIOclock. These bits should be written only if PLL is disabled.
frequency lower than or equal to 48 MHz to work correctly.
USB OTG FS clock frequency = VCO frequency / PLLQ with 2 ≤ PLLQ ≤ 15
0000: PLLQ = 0, wrong configuration
0001: PLLQ = 1, wrong configuration
0010: PLLQ = 2
0011: PLLQ = 3
0100: PLLQ = 4
...
1111: PLLQ = 15
Set and cleared by software to select PLL and PLLI2S clock source. This bit can be written
only when PLL and PLLI2S are disabled.
0: HSI clock selected as PLL and PLLI2S clock entry
1: HSE oscillator clock selected as PLL and PLLI2S clock entry
× (PLLN / PLLM)
/ PLLP
/ PLLQ
24 23 22
Res. PLLSRC
rw rw
8 7 6
rw rw rw
RM0390 Rev 4
Reset and clock control (RCC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
PLLM[5:0]
rw rw rw rw
17 16
PLLP[1:0]
rw rw
1 0
rw rw
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