Figure 24. Lse Clock Sources - STMicroelectronics STM32WLEx Reference Manual

Reset and clock control (RCC)
The LSE crystal is switched on and off using the LSEON bit in the
control register
runtime using the LSEDRV[1:0] bits in the
(RCC_BDCR)
on one side and low-power-consumption on the other side. The LSE drive can be decreased
to the lower drive capability (LSEDRV = 0) when the LSE is on. However, once LSEDRV is
selected, the drive capability can not be increased if LSEON = 1.
The LSERDY flag in the
whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not
released until this bit is set by hardware. An interrupt can be generated if enabled in the
RCC clock interrupt enable register
When enabled and ready the LSE clock can directly be used by the RTC. To be able to use
the clocks by other peripherals (LPTIMx, TIMx, USARTx, LPUARTx, system LSCO, MCO,
MSI PLL mode), the LSE system clock must be enabled with the LSESYSEN bit in the
Backup domain control register
is enabled, the LSE clock is used by the LSECSS and is available on the LSCO. A
LSESYSRDY flag is provided in the
indicate when LSE system clock is ready (due clock synchronization) after having been
enabled by the LSESYSEN.
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the
domain control register
with ~50 % duty cycle must drive the OSC32_IN pin while the OSC32_OUT pin can be used
as GPIO (see
6.2.6 LSI clock
The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby
modes for the independent watchdog (IWDG) and RTC. The clock frequency is ~32 kHz or
can be divided by 128 (~250 Hz) using LSIPRE. For more details, refer to the electrical
characteristics section of the datasheets.
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Figure 24. LSE clock sources

Clock source
Crystal/
ceramic
resonators
External
(RCC_BDCR). The crystal oscillator driving strength can be changed at
to obtain the best compromise between robustness and short start-up time
RCC Backup domain control register (RCC_BDCR)
(RCC_BDCR). When the LSE clock is ready and LSECSS
(RCC_BDCR). The external clock signal (square, sinus or triangle)
Figure 24: LSE clock
RM0461 Rev 5
Hardware configuration
OSC32_IN
C
L1
Load
capacitors
OSC32_IN
GPIO
External
clock source
RCC Backup domain control register
(RCC_CIER).
RCC Backup domain control register (RCC_BDCR)
sources).
OSC32_OUT
C
L2
OSC32_OUT
RCC Backup domain
indicates
RCC Backup
RM0461
MSv62608V1
RCC
to