Bus Grant (Bg); Bus Grant Acknowledge (Bgack); Bus Exception Control Signals; Reset (Reset) - Motorola MC68030 User Manual

5.9.2 Bus Grant (BG)
This output indicates that the MC68030 will release ownership of the bus
master when the current processor bus cycle completes. Refer to 7.7.2 Bus
Grant for more information.
5.9.3 Bus Grant Acknowledge (BGACK)
This input indicates that an external device has become the bus master. Refer
to 7.7.3 Bus Grant Acknowledge for more information.
5.10 BUS EXCEPTION CONTROL SIGNALS
The following signals are the bus exception control signals for the MC68030.
5.10.1 Reset (RESET)
This bidirectional open-drain signal is used to initiate a system reset. An
external reset signal resets the MC68030 as well as all external devices. A
reset signal from the processor (asserted as part of the RESET instruction)
resets external devices only; the internal state of the processor is not altered.
Refer to 7.8 RESET OPERATION for a description of reset bus operation and
8.1.1 Reset Exception for information about the reset exception.
5.10.2 Halt (HALT)
The halt signal indicates that the processor should suspend bus activity or,
when used with BERR, that the processor should retry the current cycle. Refer
to 7.5 BUS EXCEPTION CONTROL CYCLES for a description of the effects of
HALT on bus operations.
5.10.3 Bus Error (BERR)
The bus error signal indicates that an invalid bus operation is being attempted
or, when used with HALT, that the processor should retry the current cycle.
Refer to 7.5 BUS EXCEPTION CONTROL CYCLES for a description of the
effects of BERR on bus operations.
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MC68030 USER'S MANUAL
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