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In this case, a fetched line is stored in the fill buffer and remains valid there; the cache can
service additional read accesses from this buffer until another fill occurs or a
cache-invalidate-all operation occurs.
If ACRn[CM] indicates cache-inhibited, the controller bypasses the cache and performs an
external transfer. To ensure the consistency of cached data, execute a CPUSHL instruction
or set CACR[CINVA] to invalidate the entire cache before switching cache modes.
CPU space-register accesses, such as MOVEC, are treated as cache-inhibited.
4.5.2.4 Reset
A hardware reset clears the CACR disabling the instruction cache.
Tag array contents are not affected by reset. Accordingly,
system startup code must explicitly invalidate the cache by
setting CACR[CINVA] before the cache can be enabled.
4.5.2.5 Cache Miss Fetch Algorithm/Line Fills
As discussed in Section 4.5.1, "Instruction Cache Physical Organization," the instruction
cache hardware includes a 16-byte line-fill buffer for providing temporary storage for the
last fetched instruction.
With the cache enabled as defined by CACR[CENB], a cacheable instruction fetch that
misses in both the tag memory and the line-fill buffer generates an external fetch. The size
of the external fetch is determined by the value contained in CACR[CLNF] and the miss
address. Table 4-8 shows the relationships between the CLNF bits, the miss address, and
the size of the external fetch.
Depending on the run-time characteristics of the application and the memory response
speed, overall performance may be increased by programming CLNF to values {00, 01}.
For all cases of a line-sized fetch, the critical longword defined by miss address bits 3–2 is
accessed first followed by the remaining three longwords that are accessed by incrementing
the longword address in 0-modulo-16 increments, as shown below:
if miss address[3:2] = 00
fetch sequence = {0x0, 0x4, 0x8, 0xC}
if miss address[3:2] = 01
fetch sequence = {0x4, 0x8, 0xC, 0x0}
if miss address[3:2] = 10
fetch sequence = {0x8, 0xC, 0x0, 0x4}
if miss address[3:2] = 11
fetch sequence = {0xC, 0x0, 0x4, 0x0x8}
When an external fetch is initiated and data is loaded into the line-fill buffer, the instruction
cache maintains a special most-recently-used indicator that tracks the contents of the fill
buffer versus its corresponding cache location. At the time of the miss, the hardware
indicator is set, marking the fill buffer as most recently used. If a subsequent access occurs
NOTE:
Chapter 4. Local Memory
Instruction Cache Overview
4-11
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