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inoperable.
The MAP Switch (MAP_SW) connects MPC564 chip selects to the different external memory
banks. If memory access problems occur, the settings of these options and the associated chip
select configurations should be reviewed with some detail. Information to configure the chip
selects and memory is detailed in the following section.
1.2.5.2
Memory Bank Chip Select Configuration
Application software that executes on Reset must configure each memory bank chip select
properly for correct operation. Table 1-2 shows the default memory settings programmed by the
dBUG ROM monitor and may be applied for most user applications:
Memory Bank
CS1 = SRAM
CS1 = SRAM, asynchro-
nous access mode
CS0 = FLASH
CS0 = FLASH, asynchro-
nous access mode
CS3 = Peripheral
CS3 = Peripheral, asyn-
chronous
1.2.5.3 Reset Vector Mapping
After reset, the processor attempts to execute at physical address 0x0000_0100 if the hard reset
configuration word IP bit is cleared to 0 or physical address 0xFFF0_0100 if the hard reset
configuration word IP bit is set to 1. This requires the board to have a non-volatile memory device
in this range with the correct information stored in it. The MPC564 processor chip-select zero
(CS0) responds to any accesses after reset until the OR0 is written. Since CS0 (the global chip
select) is connected to the Flash ROM (U6), the Flash ROM initially appears at address
0xFFF0_0000. The initialization routine then programs the chip-select logic, locates the Flash
ROM to start at 0x0080_0000 and configures the rest of the internal and external peripherals.
Please refer to the MPC561/563 user's manual section 10.7 (Global (Boot) Chip-Select Operation)
for more information.
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 1-2. Chip Select Memory Options
Reg.
Default Value
BR1
0xFFF0_0003
Base Address = 0xFFF0_0000, Port width = 32 bit *Default
OR1
0xFFF0_0000
Memory Range = 0xFFF0_0000 > 0xFFF7_FFFF, wait state
BR0
0x0080_0003
Base address 0x0080_0000, Port width = 32 bit *Default
OR0
0xFFE0_0030
Memory range = 0x0080_0000 > 0x009F_FFFF, wait state
= 3, asynchronous operation 40Mhz clock, 95ns device.
Note U4 = 2M bytes and will mirror 2x with this setting.
Usable range = 0x0080_0000 > 0x008F_FFFF (dBUG mon-
itor is in upper half starting at 0x0090_0000)
BR3
0x0100_0807
Base address = 0x0100_0000, Port width = 16 bit *Default
OR3
0xFFFF_80F0
Memory Range 0x0100_0000 > 0100_7FFF, wait state =
External Terminate (TA*) *Default Note Peripheral memory
map.
Chapter 1. MPC564EVB Board
Notes
= 0. Note U2 = 512K bytes and will mirror 4x with this set-
ting. Usable range = 0xFFF0_8000 – 0xFFF7_FFFF.
External TA* generation provided.
System Memory
1-7
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