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TIER5—Timer Interrupt Enable Register 5
Bit
:
7
TTGE
Initial value
:
0
Read/Write
:
R/W
A/D Conversion Start Request Enable
0
1
6
5
4
TCIEU
TCIEV
1
0
0
R/W
R/W
Overflow Interrupt Enable
0
1
Underflow Interrupt Enable
0
Interrupt request (TCIU) by TCFU disabled
1
Interrupt request (TCIU) by TCFU enabled
A/D conversion start request generation disabled
A/D conversion start request generation enabled
H'FEA4
3
2
0
0
Interrupt request (TCIV) by TCFV disabled
Interrupt request (TCIV) by TCFV enabled
Rev. 5.00, 12/03, page 961 of 1088
1
0
TGIEB
TGIEA
0
0
R/W
R/W
TGR Interrupt Enable A
0
Interrupt request (TGIA)
by TGFA bit disabled
1
Interrupt request (TGIA)
by TGFA bit enabled
TGR Interrupt Enable B
0
Interrupt request (TGIB)
by TGFB bit disabled
1
Interrupt request (TGIB)
by TGFB bit enabled
TPU5
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