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BCRH—Bus Control Register H
Bit
:
7
ICIS1
Initial value
:
1
Read/Write
:
R/W
Idle Cycle Insert 1
Idle cycle not inserted in case of successive external read cycles in different areas
0
Idle cycle inserted in case of successive external read cycles in different areas
1
6
5
ICIS0
BRSTRM
1
0
R/W
R/W
Burst Cycle Select 1
0
1
Area 0 Burst ROM Enable
0
Basic bus interface
1
Burst ROM interface
Idle Cycle Insert 0
Idle cycle not inserted in case of successive external read and external write cycles
0
Idle cycle inserted in case of successive external read and external write cycles
1
H'FED4
4
3
BRSTS1
BRSTS0
1
0
R/W
R/W
Only 0 should be written to these bits
Burst Cycle Select 0
0
Max. 4 words in burst access
1
Max. 8 words in burst access
Burst cycle comprises 1 state
Burst cycle comprises 2 states
Rev. 5.00, 12/03, page 971 of 1088
Bus Controller
2
1
0
0
0
0
R/W
R/W
R/W
Reserved
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