Sw Debug Port; Sw Protocol Introduction; Sw Protocol Sequence; Table 221. 32-Bit Debug Port Registers Addressed Through The Shifted Value A[3:2] - ST STM32F101 series Reference Manual

RM0008

Table 221. 32-bit debug port registers addressed through the shifted value A[3:2]

Address A(3:2) value
0x0
0x4
0x8
0xC
31.8

SW debug port

31.8.1

SW protocol introduction

This synchronous serial protocol uses two pins:
•
SWCLK: clock from host to target
•
SWDIO: bidirectional
The protocol allows two banks of registers (DPACC registers and APACC registers) to be
read and written to.
Bits are transferred LSB-first on the wire.
For SWDIO bidirectional management, the line must be pulled-up on the board (100 KΩ
recommended by ARM
Each time the direction of SWDIO changes in the protocol, a turnaround time is inserted
where the line is not driven by the host nor the target. By default, this turnaround time is one
bit time, however this can be adjusted by configuring the SWCLK frequency.
31.8.2

SW protocol sequence

Each sequence consist of three phases:
1. Packet request (8 bits) transmitted by the host
2. Acknowledge response (3 bits) transmitted by the target
3. Data transfer phase (33 bits) transmitted by the host or the target
00 Reserved, must be kept at reset value.
DP CTRL/STAT register. Used to:
– Request a system or debug power-up
01 – Configure the transfer operation for AP accesses
– Control the pushed compare and pushed verify operations.
– Read some status flags (overrun, power-up acknowledges)
DP SELECT register: Used to select the current access port and the
active 4-words register window.
– Bits 31:24: APSEL: select the current AP
10 – Bits 23:8: reserved
– Bits 7:4: APBANKSEL: select the active 4-words register window on the
current AP
– Bits 3:0: reserved
DP RDBUFF register: Used to allow the debugger to get the final result
11 after a sequence of operations (without requesting new JTAG-DP
operation)
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Debug support (DBG)
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