ST STM32F101 series Reference Manual page 1093

Debug support (DBG)
Bit 9 DBG_WWDG_STOP: Debug window watchdog stopped when core is halted
Bit 8 DBG_IWDG_STOP: Debug independent watchdog stopped when core is halted
Bits 7:5 TRACE_MODE[1:0] and TRACE_IOEN: Trace pin assignment control
– With TRACE_IOEN=0:
– With TRACE_IOEN=1:
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 DBG_STANDBY: Debug Standby mode
Bit 1 DBG_STOP: Debug Stop mode
Bit 0 DBG_SLEEP: Debug Sleep mode
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0: The window watchdog counter clock continues even if the core is halted
1: The window watchdog counter clock is stopped when the core is halted
0: The watchdog counter clock continues even if the core is halted
1: The watchdog counter clock is stopped when the core is halted
TRACE_MODE=xx: TRACE pins not assigned (default state)
– TRACE_MODE=00: TRACE pin assignment for Asynchronous Mode
– TRACE_MODE=01: TRACE pin assignment for Synchronous Mode with a
TRACEDATA size of 1
– TRACE_MODE=10: TRACE pin assignment for Synchronous Mode with a
TRACEDATA size of 2
– TRACE_MODE=11: TRACE pin assignment for Synchronous Mode with a
TRACEDATA size of 4
0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
From software point of view, exiting from Standby is identical than fetching reset vector
(except a few status bit indicated that the MCU is resuming from Standby)
1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and
HCLK are provided by the internal RC oscillator which remains active. In addition, the MCU
generate a system reset during Standby mode so that exiting from Standby is identical than
fetching from reset
0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all clocks (including
HCLK and FCLK). When exiting from STOP mode, the clock configuration is identical to the
one after RESET (CPU clocked by the 8 MHz internal RC oscillator (HSI)). Consequently,
the software must reprogram the clock controller to enable the PLL, the Xtal, etc.
1: (FCLK=On, HCLK=On) In this case, when entering STOP mode, FCLK and HCLK are
provided by the internal RC oscillator which remains active in STOP mode. When exiting
STOP mode, the software must reprogram the clock controller to enable the PLL, the Xtal,
etc. (in the same way it would do in case of DBG_STOP=0)
0: (FCLK=On, HCLK=Off) In Sleep mode, FCLK is clocked by the system clock as
previously configured by the software while HCLK is disabled.
In Sleep mode, the clock controller configuration is not reset and remains in the previously
programmed state. Consequently, when exiting from Sleep mode, the software does not
need to reconfigure the clock controller.
1: (FCLK=On, HCLK=On) In this case, when entering Sleep mode, HCLK is fed by the same
clock that is provided to FCLK (system clock as previously configured by the software).
DocID13902 Rev 15
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