ST STM32F101 series Reference Manual page 1092

RM0008
DBGMCU_CR register
Address: 0xE004 2004
Only 32-bit access supported
POR Reset: 0x0000 0000 (not reset by system reset)
31 30 29
DBG_ DBG_
TIM11 TIM10
_ _
Res.
STOP STOP
rw rw
15 14 13
DBG_
DBG_I2C1 DBG_
CAN1
_SMBUS_ TIM4_
_
TIMEOUT STOP
STOP
rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:25 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=9..14)
Bits 24:22
Bit 21 DBG_CAN2_STOP: Debug CAN2 stopped when core is halted
Bits 20:17 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=8..5)
Bit 16 DBG_I2C2_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted
Bit 15 DBG_I2C1_SMBUS_TIMEOUT: SMBUS timeout mode stopped when Core is halted
Bit 14 DBG_CAN1_STOP: Debug CAN1 stopped when Core is halted
Bits 12:11 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=4..1)
28 27 26 25
DBG_ DBG_
DBG_ DBG_
TIM14 TIM13
TIM9_ TIM12_
_ _
STOP STOP
STOP STOP
rw rw rw rw
12 11 10 9
DBG_
DBG_ DBG_ DBG_
WWDG
TIM3_ TIM2_ TIM1_
_
STOP STOP STOP
STOP
rw rw rw rw
0: The clock of the involved timer counter is fed even if the core is halted, and the outputs
behave normally.
1: The clock of the involved timer counter is stopped when the core is halted, and the
outputs are disabled (as if there were an emergency stop in response to a break event).
Reserved, must be kept at reset value.
0: Same behavior as in normal mode
1: CAN2 receive registers are frozen
0: The clock of the involved timer counter is fed even if the core is halted, and the outputs
behave normally.
1: The clock of the involved timer counter is stopped when the core is halted, and the
outputs are disabled (as if there were an emergency stop in response to a break event).
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
0: Same behavior as in normal mode
1: CAN1 receive registers are frozen
0: The clock of the involved Timer Counter is fed even if the core is halted
1: The clock of the involved Timer counter is stopped when the core is halted
24 23 22
DGB_C
AN2_S
Reserved
TOP
8 7 6
DBG_ TRACE_ TRACE
IWDG MODE
STOP [1:0] IOEN
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DocID13902 Rev 15
Debug support (DBG)
21 20 19 18
DBG_ DBG_ DBG_
TIM7_ TIM6_ TIM5_
STOP STOP STOP
rw rw rw rw
5 4 3 2
DBG_
_ STAND
Reserved
BY
rw rw
17 16
DBG_ DBG_I2C2
TIM8_ _SMBUS_
STOP TIMEOUT
rw rw
1 0
DBG_ DBG_
STOP SLEEP
rw rw
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