ST STM32F101 series Reference Manual page 1060

RM0008
Ethernet DMA missed frame and buffer overflow counter register
(ETH_DMAMFBOCR)
Address offset: 0x1020
Reset value: 0x0000 0000
The DMA maintains two counters to track the number of missed frames during reception.
This register reports the current value of the counter. The counter is used for diagnostic
purposes. Bits [15:0] indicate missed frames due to the STM32F107xx buffer being
unavailable (no receive descriptor was available). Bits [27:17] indicate missed frames due to
Rx FIFO overflow conditions and runt frames (good frames of less than 64 bytes).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
rc_ rc_ rc_ rc_
r r r r
Bits 31:29 Reserved, must be kept at reset value.
Bit 28 OFOC: Overflow bit for FIFO overflow counter
Bits 27:17 MFA: Missed frames by the application
Indicates the number of frames missed by the application
Bit 16 OMFC: Overflow bit for missed frame counter
Bits 15:0 MFC: Missed frames by the controller
Indicates the number of frames missed by the Controller due to the host receive buffer being
unavailable. This counter is incremented each time the DMA discards an incoming frame.
Ethernet DMA current host transmit descriptor register (ETH_DMACHTDR)
Address offset: 0x1048
Reset value: 0x0000 0000
The Current host transmit descriptor register points to the start address of the current
transmit descriptor read by the DMA.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Bits 31:0 HTDAP: Host transmit descriptor address pointer
Ethernet DMA current host receive descriptor register (ETH_DMACHRDR)
Address offset: 0x104C
Reset value: 0x0000 0000
The Current host receive descriptor register points to the start address of the current receive
descriptor read by the DMA.
Ethernet (ETH): media access control (MAC) with DMA controller
rc_ rc_ rc_ rc_ rc_ rc_ rc_
r r r r r r
r r r r r r
Cleared . Pointer updated by DMA during operation.
DocID13902 Rev 15
rc_ rc_ rc_ rc_ rc_ rc_
r r r r r r r
HTDAP
r r r r r r r
9 8 7 6 5
MFC
rc_ rc_ rc_ rc_ rc_ rc_ rc_
r r r r r r r
9 8 7 6 5
r r r r r r r
4 3 2 1 0
rc_ rc_ rc_ rc_ rc_
r r r r r
4 3 2 1 0
r r r r r
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