ST STM32F101 series Reference Manual page 1069

Debug support (DBG)
JTMS/
SWDIO
JTDI
JTDO/
TRACESWO
NJTRST
JTCK/
SWCLK
Note: The debug features embedded in the Cortex
Design Kit.
The ARM
•
SWJ-DP: Serial wire / JTAG debug port
•
AHP-AP: AHB access
•
ITM: Instrumentation trace macrocell
•
FPB: Flash patch breakpoint
•
DWT: Data watchpoint trigger
• TPUI: Trace port unit interface (available on larger packages, where the corresponding
pins are mapped)
•
ETM: Embedded Trace Macrocell (available on larger packages, where the
corresponding pins are mapped)
It also includes debug features dedicated to the STM32F10xxx:
•
Flexible debug pinout assignment
•
MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on debug functionality supported by the ARM
refer to the Cortex
r1p0 TRM (see
1069/1128
Figure 360. Block diagram of STM32 MCU and Cortex
STM32 MCU debug support
Cortex-M3 debug support
Cortex-M3
Core
SWJ-DP
AHB-AP
Internal private
peripheral bus (PPB)
® ®
Cortex -M3 core provides integrated on-chip debug support. It is comprised of:
ort
p
®
-M3-r1p1 Technical Reference Manual and to the CoreSight Design Kit-
Section 31.2: Reference ARM®
DocID13902 Rev 15
debug support
Bus matrix
Data
External private
peripheral bus (PPB)
Bridge
NVIC
DWT
FPB
ITM
®
-M3 core are a subset of the ARM
documentation).
RM0008
®
-M3-level
DCode
interface
System
interface
ETM
TRACESWO
Trace port
TRACECK
TPIU
TRACED[3:0]
DBGMCU
®
CoreSight
® ®
Cortex -M3 core,
ai17138