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7.2.5.1 Address Acknowledge (AACK)-Input
The address acknowledge (AACK) signal is an input-only signal on the MPC750.
Following are the state meaning and timing comments for the AACK signal.
State Meaning
Asserted-Indicates that the address phase of a transaction is
complete. The address bus will go to a high-impedance state on the
next bus clock cycle. The MPC750 samples ARTRY on the bus clock
cycle following the assertion of AACK.
Negated-(During ABB) indicates that the address bus and the
transfer attributes must remain driven.
Timing Comments Assertion-May occur as early as the bus clock cycle after TS is
asserted; assertion can be delayed to allow adequate address access
time for slow devices. For example, if an implementation supports
slow snooping devices, an external arbiter can postpone the assertion
ofAACK.
Negation-Must occur one bus clock cycle after the assertion of
AACK.
7.2.5.2 Address Retry (ARTRY)
The address retry (ARTRY) signal is both an input and output signal on the MPC750.
7.2.5.2.1 Address Retry (ARTRY)-Output
Following are the state meaning and timing comments for the ARTRY output signal.
State Meaning
Asserted-Indicates that the MPC750 detects a condition in which a
snooped address tenure must be retried. If the MPC750 needs to
update memory as a result of the snoop that caused the retry, the
MPC750 asserts BR the second cycle after AACK if ARTRY is
asserted.
High Impedance-Indicates that the MPC750 does not need the
snooped address tenure to be retried.
Timing Comments Assertion-Asserted the third bus cycle following the assertion of
TS if a retry is required.
7-14
Negation-Occurs the second bus cycle after the assertion of AACK.
Since this signal may be simultaneously driven by multiple devices,
it negates in a unique fashion. First the buffer goes to high impedance
for a minimum of one-half processor cycle (dependent on the clock
mode), then it is driven negated for one bus cycle before returning to
high impedance.
This special method of negation may be disabled by setting
precharge disable in BlDO.
MPC750 RiSe Microprocessor User's Manual
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