Cache Control Signals; Cache Inhibit Input (Ciin); Cache Inhibit Output (Clodf); Cache Burst Request (Cbreq) - Motorola MC68030 User Manual

5.7 CACHE CONTROL SIGNALS
The following signals relate to the on-chip caches.
5.7.1 Cache Inhibit Input (CIIN)
This input signal prevents data from being loaded into the MC68030 instruc-
tion and data caches. It is a synchronous input signal and is interpreted on
a bus-cycle-by-bus-cycle basis. CIIN is ignored during all write cycles. Refer
to 6.1 ON-CHIP CACHE ORGANIZATION AND OPERATION for information
on the relationship of CIIN to the on-chip caches.
5.7.2 Cache Inhibit Output (ClOUT)
This three-state output signal reflects the state of the CI bit in the address
translation cache entry for the referenced logical address, indicating that an
external cache should ignore the bus transfer. When the referenced logical
address is within an area specified for transparent translation, the CI bit of
the appropriate transparent translation register controls the state of ClOUT.
Refer to SECTION 9 MEMORY MANAGEMENT UNIT for more information
about the address translation cache and transparent translation. Also, refer
to SECTION 6 ON-CHIP CACHE MEMORIES for the effect of ClOUT on the
internal caches.
5.7.3 Cache Burst Request (CBREQ)
This three-state output signal requests a burst mode operation to fill a line
in the instruction or data cache. Refer to 6.1.3 Cache Filling for filling infor-
mation and 7.3.7 Burst Operation Cycles for bus cycle information pertaining
to burst mode operations.
5.7.4 Cache Burst Acknowledge (CBACK)
This input signal indicates that the accessed device can operate in the burst
mode and can supply at least one more long word for the instruction or data
cache. Refer to 7.3.7 Burst Operation Cycles for information about burst mode
operation.
MOTOROLA MC68030 USER'S MANUAL 5-7