Table of Contents
Advertisement
7.2 Signal Descriptions
This section describes individual MPC750 signals, grouped according to Figure 7-1. Note
that the following sections summarize signal functions. Chapter 8, "SystelP Interface
Operation," describes many of these signals in greater detail, both with respect to how
individual signals function and how groups of signals interact.
7.2.1 Address Bus Arbitration Signals
The address arbitration signals are input and output signals the MPC750 uses to request the
address bus, recognize when the request is granted, and indicate to other devices when
mastership is granted. For a detailed description of how these signals interact, see
Section 8.3.1, "Address Bus Arbitration."
7.2.1.1 Bus Request (BR)-Output
Following are the state meaning and timing comments for the BR output signal.
State Meaning
Asserted-Indicates that the MPC750 is requesting mastership of
the address bus. Note that BR may be asserted for one or more
cycles, and then de-asserted due to an internal cancellation of the bus
request (for example, due to a load hit in the touch load buffer). See
Section 8.3.1, "Address Bus Arbitration."
Negated-Indicates that the MPC750 is not requesting the address
bus. The MPC750 may have no bus operation pending, it may be
parked, or the ARTRY input was asserted on the previous bus clock
cycle.
Timing Comments Assertion-Occurs when the MPC750 is not parked and a bus
transaction is needed. This may occur even if the two possible
pipeline accesses have occurred. BR will also be asserted for one
cycle during the execution of a dcbz instruction, and during the
execution of a load instruction which hits in the touch load buffer.
Negation-Occurs for at least one bus clock cycle after an accepted,
qualified bus grant (see BG and ABB), even if another transaction is
pending. It is also negated for at least one bus clock cycle when the
assertion of ARTRY is detected on the bus.
7.2.1.2 Bus Grant (BG)-Input
Following are the state meaning and timing comments for the BG input signal.
State Meaning
7-4
Asserted-Indicates that the MPC750 may, with proper
qualification, assume mastership of the address bus. A qualified bus
grant occurs when BG is asserted and ABB and ARTRY are not
asserted the bus cycle following the assertion of AACK. The ABB
and ARTRY signals are driven by the MPC750 or other bus masters.
If the MPC750 is parked, BR need not be asserted for the qualified
bus grant. See Section 8.3.1, ''Address Bus Arbitration."
MPC750 RISC Microprocessor User's Manual
Advertisement
Table of Contents
