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The PowerPC architecture consists of the following layers, and adherence to the PowerPC
architecture can be described in terms of which of the following levels of the architecture
is implemented:
PowerPC user instruction set architecture (UISA)-Defines the base user-level
instruction set, user-level registers, data types, floating-point exception model,
memory models for a uniprocessor environment, and programming model for a
uniprocessor environment.
•
PowerPC virtual environment architecture (VEA)-Describes the memory model
for a multiprocessor environment, defines cache control instructions, and describes
other aspects of virtual environments. Implementations that conform to the VEA
also adhere to the UISA, but may not necessarily adhere to the OEA.
•
PowerPC operating environment architecture (OEA)-Defines the memory
management model, supervisor-level registers, synchronization requirements, and
the exception model. Implementations that conform to the OEA also adhere to the
UISA and the VEA.
The PowerPC architecture allows a wide range of designs for such features as cache and
system interface implementations. The MPC750 implementations support the three levels
of the architecture described above. For more information about the PowerPC architecture,
see PowerPC Microprocessor Family: The Programming Environments.
Specific features of the MPC750 are listed in Section 1.2, "MPC750 Microprocessor
Features."
1.4 PowerPC Registers and Programming Model
The PowerPC architecture defines register-to-register operations for most computational
instructions. Source operands for these instructions are accessed from the registers or are
provided as immediate values embedded in the instruction opcode. The three-register
instruction format allows specification of a target register distinct from the two source
operands. Load and store instructions transfer data between registers and memory.
PowerPC processors have two levels of privilege-supervisor mode of operation (typically
used by the operating system) and user mode of operation (used by the application
software). The programming models incorporate 32 GPRs, 32 FPRs, special-purpose
registers (SPRs), and several miscellaneous registers. Each PowerPC microprocessor also
has its own unique set of hardware implementation-dependent (HID) registers.
Having access to privileged instructions, registers, and other resources allows the operating
system to control the application environment (providing virtual memory and protecting
operating-system and critical machine resources). Instructions that control the state of the
processor, the address translation mechanism, and supervisor registers can be executed only
when the processor is operating in supervisor mode.
Chapter 1. Overview
1-21
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