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10.4.6.5 Last Data In to PrechargeÑWrite Recovery
This parameter, controlled by P/LSDMR[WRC], deÞnes the earliest timing for
command after the last data was written to the SDRAM.
Activate
CLK
ALE
CS
SDRAS
SDCAS
WE
MA[0Ð11]
Row
DQM
Data
10.4.6.6 Refresh Recovery Interval (RFRC)
This parameter, controlled by P/LSDMR[RFRC], deÞnes the earliest timing for an
command after a
ACTIVATE
CLK
ALE
CS
SDRAS
SDCAS
A8 = 1
MA[0Ð11]
WE
DQM
Precharge
if needed
10.4.6.7 External Address Multiplexing Signal
In 60x-compatible mode, external address multiplexing is placed on the address lines. If the
additional delay of multiplexing is endangers the device setup time, P/LSDMR[EAMUX]
MOTOROLA
WRITE
Column
D0
D1
Figure 10-24. WRC = 2 (2 Clock Cycles)
command.
REFRESH
PRETOACT = 3
Auto refresh
Figure 10-25. RFRC = 4 (6 Clock Cycles)
Chapter 10. Memory Controller
Part III. The Hardware Interface
Last data in
Deactivate
WRC = 2
D2
D3
RFRC = 4 (6 clocks)
PRECHARGE
RAx
Activate command
Bank A
10-41
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