General Description; Figure 1-1. Mc68302 Block Diagram; Mc68000/Mc68008 Core - Motorola MC68302 User Manual

General Description

M68000 BUS
INTERRUPT
CONTROLLER
1 CHANNEL
IDMA
DRAM
REFRESH
CONTROLLER
6 CHANNELS
SDMA
MAIN
CONTROLLER
(RISC)
1-2

MC68000/MC68008 CORE

ON-CHIP PERIPHERALS BUS INTERFACE UNIT
1152 BYTES
BUS ARBITER
DUAL-PORT
STATIC RAM
3 TIMERS
PARALLEL I/O
PERIPHERAL BUS
SMC (2) SCC1
SERIAL CHANNELS PHYSICAL INTERFACE
I/O PORTS AND PIN ASSIGNMENTS

Figure 1-1. MC68302 Block Diagram

MC68302 USER'S MANUAL
MC68000 / MC68008 CORE
CHIP-SELECT
SYSTEM
AND WAIT-
CONTROL
STATE LOGIC
CLOCK
GENERATOR
SYSTEM INTEGRATION BLOCK
SCC2 SCC3
COMMUNICATIONS PROCESSOR
SCP
MOTOROLA