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Part II. ConÞguration and Reset
Bits
0
1
2
Field
Reset
R/W
Addr
Bits
16
17
18
Field
Reset
R/W
Addr
Figure 4-37. Time Counter Alarm Register (TMCNTAL)
Table 4-20 describes TMCNTAL Þelds.
Bits
Name
0Ð31 ALARM The alarm interrupt is generated when ALARM Þeld matches the corresponding TMCNT bits. The
resolution of the alarm is 1 second.
4.3.3 Periodic Interrupt Registers
The periodic interrupt registers are described in the following sections.
4.3.3.1 Periodic Interrupt Status and Control Register (PISCR)
The periodic interrupt status and control register (PISCR), shown in Figure 4-38, contains
the interrupt request level and the interrupt status bit. It also contains the controls for the 16
bits to be loaded in a modulus counter.
Bits
0
1
2
Field
Reset
R/W
Addr
Figure 4-38. Periodic Interrupt Status and Control Register (PISCR)
4-42
3
4
5
6
7
19
20
21
22
23
Table 4-20. TMCNTAL Field Descriptions
3
4
5
6
Ñ
0000_0000_0000_0000
MPC8260 PowerQUICC II UserÕs Manual
8
9
10
11
ALARM
Ñ
R/W
0x1022C
24
25
26
27
ALARM
Ñ
R/W
0x1222E
Description
7
8
9
10
PS
Ñ
R/W
0x10240
12
13
14
28
29
30
11
12
13
14
PIE
PTF
PTE
MOTOROLA
15
31
15
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