Table of Contents
Advertisement
Arc Four Execution Unit Registers
If the key length is not divisible by four, the lower key data
registers must be filled before writing to the upper key data
registers.
5.1.6 Message Byte Double-Word Register
The Message Byte Double-Word Register is a 3-bit write-only register and is used to hold
the number of bytes (minus one) in the last/partial sub-message. A 1 in the MSB of this
register indicates to the AFEU that this is the last sub-message. Figure 5-3 shows the
Message Byte Double-Word Register. The default number of sub-message bytes is four.
0
Field
Reset
R/W
Addr
1
Setting the Last Sub-message bit in this register will cause the AFEU to reset and start initializing once the full
message is complete. The contents of the cipher register will hold the last processed sub-message.
Figure 5-3. Arc Four Execution Unit Message Byte Double-Word Register
5.1.7 Message Register
The Message Register is a 32-bit write-only register that stores the sub-message to be
processed. This can either be the plaintext to be encrypted or ciphertext to be decrypted.
Writing data to this register signals the AFEU to start processing the data.
5.1.8 Cipher Register
The Cipher Register is a 32-bit read-only register that stores the processed sub-message.
This can either be the encrypted ciphertext or decrypted plaintext. Data in this register is
valid when the sub- or full message done bit is set in the status register.
If the sub-message is less than 32-bits, the unused bits in the
Cipher Register will be the same as the corresponding bits
written to the Message Register.
5-4
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE:
—
0000_0000_0000_0000
W
0x408
NOTE:
MPC180E Security Processor User's Manual
28
29
1
Last
sub-message
30
31
# sub-message
bytes - 1
Advertisement
Table of Contents
