Cache Interactions - Motorola MC68030 User Manual

Bus Operation

7.2.7 Cache Interactions

The organization and requirements of the on-chip instruction and data caches affect the
interpretation of the DSACKx and STERM signals. Since the MC68030 attempts to load all
data operands and instructions that are cachable into the on-chip caches, the bus may
operate differently when caching is enabled. Specifically, on cachable read cycles that
terminate normally, the low-order address signals (A0 and A1) and the size signals do not
apply.
The slave device must supply as much aligned data on the data bus as its port size allows,
regardless of the requested operand size. This means that an 8-bit port must supply a byte,
a 16-bit port must supply a word, and a 32-bit port must supply an entire long word. This
data is loaded into the cache. For a 32-bit port, the slave device ignores A0 and A1 and
supplies the long word beginning at the long-word boundary on the data bus. For a 16-bit[lz
port, the device ignores A0 and supplies the entire word beginning at the lower word
boundary on D16–D31 of the data bus. For a byte port, the device supplies the addressed
byte on D24–D31.
If the addressed device cannot supply port-sized data or if the data should not be cached,
the device must assert cache inhibit in (CIIN) as it terminates the read cycle. If the bus cycle
terminates abnormally, the MC68030 does not cache the data. For details of interactions of
port sizes, misalignments, and cache filling, refer to 6.1.3 Cache Filling.
The caches can also affect the assertion of AS and the operation of a read cycle. The search
of the appropriate cache by the processor begins when the microsequencer requires an
instruction or a data item. At this time, the bus controller may also initiate an external bus
cycle in case the requested item is not resident in the instruction or data cache. If the bus is
not occupied with another read or write cycle, the bus controller asserts the ECS signal (and
the OCS signal, if appropriate). If an internal cache hit occurs, the external cycle aborts, and
AS is not asserted. This makes it possible to have ECS asserted on multiple consecutive
clock cycles. Notice that there is a minimum time specified from the negation of ECS to the
next assertion of ECS (refer to MC68030EC/D, MC68030 Electrical Specifications .
Instruction prefetches can occur every other clock so that if, after an aborted cycle due to an
instruction cache hit, the bus controller asserts ECS on the next clock, this second cycle is
for a data fetch. However, data accesses that hit in the data cache can also cause the
assertion of ECS and an aborted cycle. Therefore, since instruction and data accesses are
mixed, it is possible to see multiple successive ECS assertions on the external bus if the
processor is hitting in both caches and if the bus controller is free. Note that, if the bus
controller is executing other cycles, these aborted cycles due to cache hits may not be seen
externally. Also, OCS is asserted for the first external cycle of an operand transfer.
Therefore, in the case of a misaligned data transfer where the first portion of the operand
results in a cache hit (but the bus controller did not begin an external cycle and then abort
it) and the second portion in a cache miss, OCS is asserted for the second portion of the
operand.
MOTOROLA MC68030 USER'S MANUAL 7-25