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7.2.7.1.2 Data Bus (DH[O-31], DL[O-31]}-lnput
Following are the state meaning and timing comments for the DH and DL input signals.
State Meaning
AssertedlNegated-Represents the state of data during a data read
transaction.
Timing Comments Assertion/Negation-Data must be valid on the same bus clock cycle
that TA is asserted.
7.2.7.2 Data Bus Parity (DP[O-7])
The eight data bus parity (DP[O-7]) signals on the MPC7S0 are both output and input
signals.
7.2.7.2.1 Data Bus Parity (DP[O-7])-Output
Following are the state meaning and timing comments for the DP output signals.
State Meaning
Asserted/Negated-Represents odd parity for each of the 8 bytes of
data write transactions. Odd parity means that an odd number of bits,
including the parity bit, are driven high. The generation of parity is
enabled through HIDO. The signal assignments are listed in
Table 7-5.
Timing Comments AssertionlNegation-The same as DL[0-31).
High Impedance-The same as DL[O-31].
Table 7-5. DP[O-7] Signal Assignments
Signal Name
Signal Assignments
DPO
DH[O-7]
DP1
DH[S-1S]
DP2
DH[16-23]
DP3
DH[24-31]
DP4
DL[O-7]
DPS
DL[S-15]
DP6
DL[16-23]
DP7
DL[24-31]
7.2.7.2.2 Data Bus Parity (DP[O-7])-lnput
Following are the state meaning and timing comments for the DP input signals.
State Meaning
AssertedlNegated-Represents odd parity for each byte of read data.
Parity is checked on all data byte lanes, regardless of the size of the
transfer. Detected even parity causes a checks top if data parity errors
are enabled in the HIDO register.
Timing Comments Assertion/Negation-The same as DL[O-31).
7-18
MPC750 RISC Microprocessor User's Manual
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