Pipelined Architecture; The Cache Memories - Motorola MC68030 User Manual

into fixed-size pages that contain the same number of bytes as the page
frames. Memory management assigns a physical base address to a logical
page. The system software then transfers data between secondary storage
and memory one or more pages at a time.
1.8 PIPELINED ARCHITECTURE
The MC68030 uses a three-stage pipelined internal architecture to provide
for optimum instruction
throug~put.
The pipeline allows as many as three
words of a single instruction or three consecutive instructions to be decoded
concurrently.
1.9 THE CACHE MEMORIES
1-16
Due to locality of reference, instructions and data that are used in a program
have a high probability of being reused within a short time. Additionally,
instructions and data operands that reside in proximity to the instructions
and data currently in use also have a high probability of being utilized within
a short period. To exploit these locality characteristics, the MC68030 contains
two on-chip logical caches, a data cache, and an instruction cache.
Each of the caches stores 256 bytes of information, organized as 16 entries,
each containing a block of four long words (16 bytes). The processor fills the
cache entries either one long word at a time or, during burst mode accesses,
four long words consecutively. The burst mode of operation not only fills
the cache efficiently but also captures adjacent instruction or data items that
are likely to be required in the near future due to locality characteristics of
the executing task.
The caches improve the overall performance of the system by -reducing the
number of bus cycles required by the processor to fetch information from
memory and by increasing the bus bandwidth available for other bus masters
in the system. Addition of the data cache in the MC68030 extends the benefits
of cache techniques to all memory accesses. During a write cycle, the data
cache circuitry writes data to a cached data item as well as to the item in
memory, maintaining consistency between data in the cache and that in
memory. However, writing data that is not in the cache mayor may not cause
the data item to be stored in the cache, depending on the write allocation
policy selected in the cache control register (CACR).
MC68030 USER'S MANUAL MOTOROLA