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Table 2-52 describes the memory synchronization instructions defined by the VEA.
Table 2-52. Memory Synchronization Instructions-VEA
Name
Mnemonic Syntax
Implementation Notes
Enforce
eieio
-
The eieio instruction is dispatched to the LSU and executes after all previous
In·Order
cache·inhibited or write-through accesses are performed; all subsequent
Execution
instructions that generate such accesses execute after eieio.lf HIDO[ABE]
=
1 an
of I/O
EIEIO operation is broadcast on the external bus to enforce ordering in the
external memory system. The eieio operation bypasses the L2 cache and is
forwarded to the bus unit. If HIDO[ABE]
=
0, the operation is not broadcast.
Because the MPC750 does not reorder noncacheable accesses, eieio is not
needed to force ordering. However, if store gathering is enabled and an eieio is
detected in a store queue, stores are not gathered. If HIDO[ABE]
=
1,
broadcasting eieio prevents external devices, such as a bus bridge chip, from
gathering stores.
Instruction
isync
-
The isync instruction is refetch serializing; that is, it causes the MPC750 to purge
Synchronize
its instruction queue and wait for all prior instructions to complete before
refetching the next instruction, which is not executed until all previous instructions
complete to the point where they cannot cause an exception. The isync
instruction does not wait for all pending stores in the store queue to complete.
Any instruction after an isync sees all effects of prior instructions.
2.3.5.3 Memory Control Instructions-VEA
Memory control instructions can be classified as follows:
• Cache management instructions (user-level and supervisor-level)
•
Segment register manipulation instructions (OEA)
• Translation lookaside buffer management instructions (OEA)
This section describes the user-level cache management instructions defined by the VEA.
See Section 2.3.6.3, "Memory Control Instructions-OEA," for information about
supervisor-level cache, segment register manipulation, and translation lookaside buffer
management instructions.
2.3.5.3.1 User-Level Cache Instructions-VEA
The instructions summarized in this section help user-level programs manage on-chip
caches if they are implemented. See Chapter 3, "LI Instruction and Data Cache Operation,"
for more information about cache topics. The following sections describe how these
operations are treated with respect to the MPC750's cache.
As with other memory-related instructions, the effects of cache management instructions
on memory are weakly-ordered. If the programmer must ensure that cache or other
instructions have been performed with respect to all other processors and system
mechanisms, a syne instruction must be placed after those instructions.
Note that the MPC750 interprets cache control instructions (icbi, debi, debf, debz, and
debst) as if they pertain only to the local L1 and L2 cache. A debz (with M set) is always
broadcast on the 60x bus. The debi, debf, and debst operations are broadcast if
HIDO[ABE]
is set.
2-62
MPC750 RISC Microprocessor User's Manual
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