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Register Name:
Register Mnemonic:
Register Function:
15
Bit
Mnemonic
RC8:0
Refresh Counter
Reload Value
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a
logic zero to ensure compatibility with future Intel products.
7.7.2.3
Refresh Control Register
Figure 7-8 shows the Refresh Control Register. The user may read or write the REN bit at any
time to turn the Refresh Control Unit on or off. The lower nine bits contain the current nine-bit
down-counter value. The user cannot program these bits. Disabling the Refresh Control Unit
clears both the counter and the corresponding counter bits in the control register.
Refresh Clock Interval Register
RFTIME
Sets refresh rate.
R
C
8
Reset
Bit Name
State
000H
Figure 7-7. Refresh Clock Interval Register
REFRESH CONTROL UNIT
R
R
R
R
R
C
C
C
C
C
7
6
5
4
3
Function
Sets the desired clock count between refresh
cycles.
0
R
R
R
C
C
C
2
1
0
A1288-0A
7-9
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