Table of Contents
Advertisement
4. Instantiating the Nios II Processor
NII-PRG | 2018.04.18
Related Information
Processor Architecture
4.7.5. CPU ID Control Register Value
In Platform Designer, the automatically-assigned CPUID control register value is
always 0x00000000, so Intel recommends always assigning the value manually.
To assign the value yourself, turn on Assign cpuid control register value manually and
type a 32-bit value (in hexadecimal or decimal format) in the cpuid control register
value box.
4.7.6. Generate Trace File
Through this selection, Platform Designer creates a trace file called
"system_name"_"cpu_name".tr
4.7.7. Exception Checking
The Exception Checking settings provide the following options:
Misaligned memory access—Misaligned memory access detection is only available
for the Nios II/f core. When Misaligned memory access is on, the processor checks for
misaligned memory accesses.
Note:
When your system contains an MMU or MPU, the processor automatically generates
misaligned memory access exceptions. Therefore, the Misaligned memory access
check box is always disabled when Include MMU or Include MPU on the Core Nios
II tab are on.
There are two misaligned memory address exceptions:
•
Misaligned data address—Data addresses of load and store instructions are
checked for misalignment. A data address is considered misaligned if the byte
address is not a multiple of the data width of the load or store instruction (4 bytes
for word, 2 bytes for half-word). Byte load and store instructions are always
aligned so never generate a misaligned data address exception.
•
Misaligned destination address—Destination instruction addresses of
,
jmp
destination instruction address is considered misaligned if the target byte address
of the instruction is not a multiple of four.
Your exception handler can use this code to quickly determine the proper action to
take, rather than have to determine the cause of an exception through instruction
decoding. Additionally, some exceptions also store the instruction or data address
associated with the exception in the
For further descriptions of exceptions, exception handling, and control registers, refer
to the Programming Model chapter of the Nios II Processor Reference Handbook.
Related Information
Programming Model
on page 14
,
, and
instructions are checked for misalignment. A
ret
eret
bret
on page 36
. Use the
nios2-trace
register.
badaddr
command to display it.
,
br
callr
Nios II Processor Reference Guide
,
119
Advertisement
Table of Contents
